Two-Stage IP De-Jitter Algorithm for Multiplexed Video Streams
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Solution Overview
Problem
Existing multiplexed systems face issues with signal disruption due to excessive bandwidth and delay in data packet delivery, particularly in time-critical video applications, where existing de-jitter techniques can cause output bandwidth to exceed limits or result in late arrival of video components.
Innovation Solution
A two-stage IP de-Jitter algorithm is implemented in a multiplexer, using a first phase locked loop for initial de-jitter operation and a second phase locked loop based on output hardware and sequence encoding, with program clock reference correction to manage packet timing and synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing de-jitter techniques are used to ensure signal quality, then signal quality is improved, but output multiplexed bandwidth exceeds the allowed bandwidth
Solution Approach 1:
The de-jitter process is divided into two distinct stages: a first de-jitter stage that handles initial timing adjustment, and a second de-jitter stage that performs refined timing correction based on program clock reference. This segmentation allows each stage to be optimized independently, preventing bandwidth exceedance while maintaining signal quality.
Solution Approach 2:
The first de-jitter operation performs preliminary timing adjustment on incoming packets before they are processed by the second de-jitter stage. This preliminary action reduces the burden on the second stage and prevents bandwidth congestion by addressing timing issues early in the processing pipeline.
2Reliability
If existing de-jitter techniques are used to ensure signal quality, then signal quality is improved, but excessive delay in delivery time occurs
Solution Approach 1:
By dividing de-jitter into two stages, the patent reduces the total processing time compared to a single comprehensive de-jitter operation. The first stage handles bulk timing adjustment quickly, while the second stage performs precise corrections with minimal delay, overall reducing the time loss while maintaining signal quality.
Solution Approach 2:
The first de-jitter stage performs preliminary timing corrections that address the majority of timing issues immediately, reducing the need for extensive processing later. This preliminary action minimizes total delay by resolving timing problems early rather than deferring them to a single later processing stage.
3Reliability
If packets are processed with strict timing requirements, then signal disruption is prevented, but device complexity increases
Solution Approach 1:
The processing system is segmented into two distinct de-jitter stages with specific functions. The first stage handles general timing adjustment, while the second stage handles program clock reference-based corrections. This segmentation simplifies the overall system design by breaking down complex timing management into manageable, dedicated stages rather than requiring a single complex processing unit.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces jitter and ensures timely delivery of multiplexed signals, maintaining signal quality and preventing bandwidth exceedance, thereby addressing the challenges of signal disruption and delay in multiplexed systems.
Implementation Method 1
performing a first de-jitter operation on each of said plurality of input signals. The system can also include determining a sequence for encoding said plurality of packets from each of said plurality of input signals into a multiplexed signal
Implementation Method 2
wherein said second de-jitter operation is accomplished using a second phase locked loop; wherein said second phase locked loop is based at least in part on output hardware associated with an output schedule time for said input signals to which said program clock reference has been applied
Implementation Method 3
determining whether any of said plurality of input signals is to be encoded incorporating a program clock reference. In some embodiments, the system can further include applying a program clock reference correction to each input signal that is to be encoded incorporation said program clock reference
Data Source
AI summary
A system and method are provided for encoding and decoding multiplexed video signals to de-jitter the content. A first de-jitter operation is performed on incoming signals and a second de-jitter operation is performed on PCR modified outbound packetized signals after sequencing of the packetized signals has been determined. In one case the second de-jitter operation can be performed using a PLL that is based, at least in part, on the output hardware limitations.