Two-Stage L2P Mapping for SSD Address Translation
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Solution Overview
Problem
Existing solid-state drives (SSDs) face inefficiencies in managing logical-to-physical address mappings, particularly due to the need for complex rebuilding of mapping tables after power failures or initial power-up, and the reliance on expensive volatile memory for storing these mappings.
Innovation Solution
Implementing a two-stage logical-to-physical (L2P) address mapping architecture using byte-rewritable memory for the first stage and block-erasable non-volatile memory for the second stage, allowing for reduced complexity and faster access times by storing the mapping table across two levels of persistent memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a traditional single-stage L2P mapping table is used stored in volatile memory, then address mapping can be performed, but the system requires expensive volatile memory and complex rebuilding processes after power failures
Solution Approach 1:
The L2P mapping table is divided into two stages: a first stage stored in byte-rewritable non-volatile memory and a second stage stored in block-erasable non-volatile memory. This segmentation allows different portions of the mapping table to be stored in memory types optimized for their specific functions, reducing the need for complex rebuilding procedures after power failures while maintaining mapping reliability.
Solution Approach 2:
The first stage of the L2P mapping table stored in byte-rewritable non-volatile memory acts as an intermediary between the host system and the second stage in block-erasable memory. This intermediary structure enables faster access to frequently used mapping entries while the second stage maintains the complete mapping information, thereby improving reliability without requiring complex full-table rebuilding operations.
2Speed
If volatile memory is used to store the L2P mapping table, then fast access is achieved, but expensive volatile memory resources are consumed
Solution Approach 1:
The patent changes the memory parameter from volatile to byte-rewritable non-volatile memory for the first stage of the L2P mapping table. This parameter change maintains fast access speeds comparable to volatile memory while eliminating the need for expensive volatile memory resources, as byte-rewritable non-volatile memory provides both speed and persistence characteristics.
3Reliability
If the L2P mapping table is stored in non-volatile memory, then power failure resilience is improved, but access time may increase
Solution Approach 1:
The mapping table is segmented into two stages with different non-volatile memory characteristics. The first stage in byte-rewritable non-volatile memory provides fast access for frequently accessed mappings, while the second stage in block-erasable non-volatile memory provides power failure resilience for the complete mapping table. This segmentation resolves the contradiction by optimizing each stage for its specific function.
Solution Approach 2:
The first stage of the L2P mapping table is pre-loaded into byte-rewritable non-volatile memory before access operations. This preliminary action ensures that frequently accessed mapping entries are already available in fast memory, eliminating access time delays while maintaining power failure resilience through the non-volatile nature of the storage medium.
Data Source
AI summary
Aspects of the present disclosure provide systems and methods for operating a solid state drive (SSD) using two-level indirection architecture. The SSD receives a command to perform a data operation in a NAND array and a logical address for the data operation. The SSD then converts the logical address to a physical address using a two-stage logical-to-physical (L2P) mapping table that includes a first stage stored in a byte-rewritable memory and a second stage stored in a block-erasable non-volatile memory (NVM). The SSD performs the data operation in the NAND array based on the physical address. The byte-rewritable memory may any byte-rewritable persistent memory. The block-erasable low latency NVM may be a flash memory that has lower latency than NAND array.