Two-Stage Level Shifter Circuit for Faster Voltage Translation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional cross-coupled level shifters face challenges in achieving high performance and low static current consumption due to larger nMOS pull-down devices requiring more current and increased parasitic capacitance, which limits data speeds and efficiency.
Innovation Solution
A two-stage high-speed voltage level shifter design that splits the level shifter into two stages with separate reference voltages and booster transistors, reducing the N-to-P device ratio and parasitic capacitance, and using overdrive control transistors to maximize overdrive voltage and reduce subthreshold current dependency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If larger nMOS pull-down devices are used in conventional cross-coupled level shifters, then voltage translation capability is improved, but static current consumption increases and parasitic capacitance increases
Solution Approach 1:
The level shifter is divided into two stages: a first stage level shifter that translates input signals from a first voltage domain to an intermediate voltage domain, and a second stage level shifter that translates the intermediate signals to a second voltage domain. This segmentation allows each stage to use smaller transistors with appropriate sizing, reducing the N-to-P device ratio and parasitic capacitance while maintaining voltage translation capability.
2Reliability
If larger nMOS pull-down devices are used in conventional cross-coupled level shifters, then voltage translation capability is improved, but data speed is limited due to increased parasitic capacitance
Solution Approach 1:
By dividing the level shifter into two stages with intermediate voltage translation, each stage can use optimally sized transistors rather than requiring one large nMOS device. This reduces the overall parasitic capacitance and allows for faster switching speeds while maintaining the required voltage translation from the first voltage domain to the second voltage domain.
Solution Approach 2:
An intermediate voltage domain is introduced as a mediator between the first and second voltage domains. The first stage level shifter translates voltages to this intermediate domain, and the second stage level shifter translates from the intermediate domain to the final voltage domain. This intermediary approach reduces the voltage translation burden on any single stage, allowing for smaller devices and reduced parasitic capacitance.
3Device complexity
If conventional cross-coupled level shifters are used, then circuit simplicity is maintained, but performance and power efficiency are limited
Solution Approach 1:
The conventional single-stage level shifter is segmented into two cascaded stages, each with its own pull-down and pull-up devices. While this increases the number of components, each stage can be independently optimized with appropriate transistor sizing, resulting in reduced N-to-P device ratio, reduced parasitic capacitance, and improved overall performance and power efficiency.
Data Source
AI summary
Improved voltage level shifters are disclosed capable of achieving substantially higher data transfer speeds with reduced static current than existing cross-coupled voltage level shifters. The voltage level shifters disclosed herein include first stage that translates input voltage signals received from a core circuitry in a first voltage domain to intermediate output voltage signals an intermediate voltage domain, and second stage circuitry that translates the intermediate output voltage signals received from the first stage circuitry in the intermediate voltage domain to output voltage signals in a second voltage domain. The disclosed voltage level shifters are scalable to support various logic voltage levels in the second voltage domain.