Two-Stage Level Shifter for Sub-1 ns Voltage Domain Switching

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Solution Overview

Problem

Existing level shifters in integrated circuits are limited by switching times greater than 1 ns and can fail with low supply voltage, unable to efficiently convert digital signals between different voltage domains.

Innovation Solution

An improved level shifter design incorporating a coupling stage and a level-switching stage, utilizing NMOS and PMOS transistors with capacitors to achieve faster switching times by oscillating node voltages between VDDL and 2*VDDL, enabling switching times below 1 ns while using the same core power supply voltages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If prior art level shifter designs are used, then the circuit structure is simple, but the switching time is greater than 1 ns

Engineering Contradiction:

Improveswitching timeVSAvoidcircuit structure

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The level shifter is divided into two distinct stages: a coupling stage with NMOS transistors (301, 302) that generates intermediate signals, and a level-switching stage with PMOS transistors (303, 304) that performs the actual voltage domain conversion. This segmentation allows each stage to be optimized independently, achieving sub-1 ns switching times while maintaining reasonable circuit complexity.

Inventive Principle:

Principle #1Segmentation

2Reliability

If low supply voltage is used, then power consumption is reduced, but the level shifter can fail altogether

Engineering Contradiction:

Improveoperation reliabilityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The invention changes the voltage parameters through the two-stage architecture. The coupling stage operates at the lower VDDL voltage domain, while the level-switching stage converts to the higher VDDH voltage domain. This parameter transformation allows the circuit to maintain reliable operation at higher voltages when needed, while the coupling stage can operate efficiently at lower voltages, balancing reliability and power consumption.

Inventive Principle:

Principle #35Parameter changes

3Speed

If the peak voltage of A and A-BAR is too low, then power consumption is reduced, but the level shifter cannot operate

Engineering Contradiction:

Improveswitching capabilityVSAvoidsupply voltage

Core Design Contradiction:

SpeedVSUse of energy by moving object

Solution Approach 1:

The coupling stage acts as an intermediary between the low-voltage input signals (A, A-BAR) and the high-voltage output signals. It conditions the low-voltage signals and generates intermediate signals that can then be properly level-shifted to the high voltage domain, enabling the level shifter to operate correctly even when input peak voltages are low.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS10804902B1Level shifter for integrated circuit

Publication Date: 2020.10.13 SILICON STORAGE TECHNOLOGY INC

AI summary

An improved level shifter for use in integrated circuits is disclosed. The level shifter is able to achieve a switching time below 1 ns while still using the core power supply voltages, VDDL and VDDH, used in the prior art. The improved level shifter comprises a coupling stage and a level-switching stage.