Two-Stage LRU Cache Replacement for High-Associativity Timing

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Solution Overview

Problem

Conventional least recently used (LRU) replacement policies in set-associative caches face challenges in fitting cache replacement operations into a single clock cycle due to increased execution time with high associativity, leading to inefficiencies in cache transactions.

Innovation Solution

Implementing a two-stage LRU replacement policy, where the first stage determines the LRU way and the second stage updates the LRU data structure, allowing operations to be performed across consecutive clock cycles, and incorporating hazard resolution mechanisms to handle overlapping transactions on the same set.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If conventional LRU replacement policy is implemented in a single clock cycle, then the cache replacement operation completes in one cycle, but the execution time increases with the number of cache lines in high associativity caches making it challenging to fit all operations in one cycle

Engineering Contradiction:
Improvecache replacement operation timeVSAvoidcache associativity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The LRU replacement policy is divided into two distinct stages: a first stage that computes the LRU way selection, and a second stage that updates the LRU data structure. This segmentation allows the complex replacement operation to be broken down into manageable steps that can be executed within clock cycle constraints, particularly for high associativity caches where a single-cycle implementation would be infeasible.

Inventive Principle:
Principle #1Segmentation

2Productivity

If two-stage LRU replacement computation is performed in consecutive clock cycles, then the cache replacement operations can be completed, but the overall transaction time increases due to spanning multiple cycles

Engineering Contradiction:
Improvecache transaction throughputVSAvoidtransaction completion time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The first stage of LRU computation is performed in advance during the current clock cycle, preparing the LRU way selection before the second stage updates the data structure in the next clock cycle. This preliminary action allows the replacement decision to be made early, enabling better pipeline utilization and reducing the impact of the two-stage process on overall transaction throughput.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If hazard resolution is performed by waiting for the second stage of previous transaction to complete, then the LRU data structure is guaranteed to be updated, but the current transaction experiences delays

Engineering Contradiction:
ImproveLRU data structure consistencyVSAvoidtransaction delay
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The hazard resolution process begins in the first stage by predicting which ways will be updated in the second stage of the previous transaction. This preliminary identification of potentially hazardous ways allows the current transaction to prepare appropriate resolution actions in advance, rather than waiting passively for the second stage to complete, thereby reducing transaction delays while maintaining data structure consistency.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The hazard resolution mechanism performs partial updates and validations in the first stage based on predicted second-stage outcomes. Rather than requiring complete confirmation of the second stage before proceeding, the system performs sufficient partial actions to ensure correctness, allowing the current transaction to continue with appropriate confidence without full waiting.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS20260086952A1Time-efficient implementation of cache replacement policy
Publication Date: 2026.03.26 GOOGLE LLC
  • US20260086952A1 patent drawing
  • US20260086952A1 patent drawing
  • US20260086952A1 patent drawing

AI summary

A cache includes multiple sets with each set having multiple respective ways, and replacement logic configured to implement a two-stage least recently used (LRU) replacement computation. The two-stage LRU replacement computation causes the cache to perform a first stage during which the cache computes an LRU way for a set, and a second stage during which the cache updates an LRU data structure with information of a transaction accessed way.