Two-Stage Memory Decoder for Low-Latency Error Correction
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Solution Overview
Problem
Non-volatile data storage devices face increased bit error rates due to higher storage density, leading to inefficiencies in error correction, particularly in terms of power consumption and latency, as existing decoding techniques struggle to balance error correction capacity with resource utilization.
Innovation Solution
A data storage device employing a preliminary bit-flipping stage followed by a low-density parity check (LDPC) decoder, utilizing redundancy information stored in unallocated redundant columns to enhance error correction performance without increasing power consumption or clock cycles, by modifying bit values based on parity check conditions and providing modified data to the second decoding stage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If iterative belief-propagation decoding techniques are used to achieve enhanced error correction capability, then error correction capability is improved, but latency and power consumption increase
Solution Approach 1:
The decoder is divided into two independent stages: a bit-flipping stage that performs preliminary error correction, and an LDPC decoding stage that handles remaining errors. This segmentation allows the system to achieve robust error correction without requiring full iterative belief-propagation decoding for all cases, thereby reducing latency while maintaining reliability.
Solution Approach 2:
The bit-flipping stage performs preliminary error correction before the main LDPC decoding process. By correcting easily detectable errors in advance, the preliminary action reduces the burden on the subsequent LDPC stage, enabling faster overall decoding with reduced latency while maintaining high error correction capability.
2Reliability
If iterative belief-propagation decoding techniques are used to achieve enhanced error correction capability, then error correction capability is improved, but power consumption increases
Solution Approach 1:
The decoding process is segmented into a low-power bit-flipping stage and an LDPC stage. The bit-flipping stage consumes significantly less power than full iterative belief-propagation decoding, yet corrects many errors preliminarily. This segmentation enables the system to achieve enhanced error correction capability with reduced overall power consumption.
Solution Approach 2:
The bit-flipping stage performs partial error correction action rather than complete iterative belief-propagation decoding. By applying a simpler, lower-power correction method that handles the majority of errors, the system achieves sufficient error correction capability without the excessive power consumption of full iterative decoding.
3Reliability
If more parity bits are used to increase error correction capacity, then error correction capacity is improved, but the number of bits required to store encoded data increases
Solution Approach 1:
The system changes the decoding parameters and methods rather than simply increasing the number of parity bits. By using the two-stage decoding approach with bit-flipping and LDPC, the system achieves high error correction capacity with the original code structure, avoiding the need to increase the total number of stored bits.
Data Source
AI summary
An apparatus includes a memory die including a group of storage elements and one or more unallocated redundant columns. A number of the unallocated redundant columns is based on a number of one or more bad columns of the memory die. The apparatus further includes a controller coupled to the memory. The controller is configured to receive data and redundancy information associated with the data from the memory. The data includes a first bit, and the redundancy information includes a second bit. The redundancy information is sensed from the one or more unallocated redundant columns and has a size that is based on the number of one or more bad columns. The controller is further configured to determine a value of the first bit based on one or more parity check conditions associated with the second bit.