Two-Stage 4:1 Multiplexer Structure for Lower Parasitic Load
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Solution Overview
Problem
High-speed 4:1 multiplexers face reduced output speed due to increased parasitic capacitors at the output terminal, which are generated by both the transistors and routing in the circuit structure.
Innovation Solution
Implementing a two-stage structure for the input terminal of the multiplexer, where the output signals from the input circuits are transmitted through additional circuits, reducing the number of parasitic capacitors and maintaining high-speed operation even with relatively slow clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If four input circuits are connected directly to the output terminal, then the multiplexer can be implemented with a simple structure, but the total parasitic capacitor at the output terminal increases and output speed decreases
Solution Approach 1:
The patent divides the direct connection structure into two stages: a first stage with four input circuits and a second stage with an output circuit. This segmentation reduces the direct parasitic capacitor connection at the output terminal by introducing an intermediate stage, thereby maintaining simpler overall structure while improving output speed.
2Speed
If a two-stage structure with addition circuit is implemented, then parasitic capacitors at the output terminal are reduced and output speed increases, but device complexity increases
Solution Approach 1:
The patent introduces an addition circuit as an intermediary stage between the input circuits and the output terminal. This intermediate addition circuit reduces the parasitic capacitor effect at the output by processing signals in stages, achieving higher speed while managing the increased structural complexity through functional decomposition.
Data Source
AI summary
A high-speed 4:1 multiplexer according to an embodiment comprises an input circuit unit including a first circuit that receives a first data as an input signal, and outputs a first output data as an output signal, a second circuit that receives a second data as an input signal, and outputs a second output data as an output signal, a third circuit that receives a third data as an input signal, and outputs a third output data as an output signal, and a fourth circuit that receives a fourth data as an input signal, and outputs a fourth output data as an output signal, a first stage for dividing the output data of the input circuit unit by two and receiving as an input signal, and outputting a first intermediate data and a second intermediate data as an output signal and a second stage of receiving the first intermediate data and the second intermediate data as an input signal and outputting a final data as an output signal.