Two-Stage Plating for Void-Free Through-Wafer Vias
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Solution Overview
Problem
Current methods for forming conductive through-wafer vias are inefficient due to slow fill rates and non-uniform plating, especially in high aspect ratio vias, leading to voids and prolonged processing times.
Innovation Solution
A two-stage plating process where the upper portion of the via is initially filled to create an enclosed volume, followed by exposing and filling the remaining portion, allowing for higher current densities and enhanced diffusion rates, thereby improving throughput and reducing processing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bottom up plating is used to fill high aspect ratio vias, then void-free via can be achieved, but the fill rate is slow and processing time is prolonged
Solution Approach 1:
The via filling process is divided into two separate stages: first filling the upper portion to create an enclosed volume, then exposing and filling the remaining lower portion. This segmentation allows each stage to be optimized independently, achieving both void-free filling and high fill rate.
Solution Approach 2:
The upper portion of the via is filled first as a preliminary action to create an enclosed volume that acts as a reservoir. This preliminary filling enables subsequent high current density plating in the second stage without compromising void-free quality, as the enclosed volume buffers the rapid metal deposition.
2Productivity
If higher plating current density is applied to increase fill rate, then processing time is reduced, but plating thickness becomes non-uniform with metal filling the upper portion before the bottom
Solution Approach 1:
The plating process is segmented into two stages with different current density regimes. The first stage uses lower current density for uniform initial filling, while the second stage uses higher current density for rapid completion after the enclosed volume is established, preventing non-uniform thickness distribution.
Solution Approach 2:
The first plating stage serves as a preliminary action that establishes a uniform metal layer and creates the enclosed volume. This preliminary structure enables the second stage to safely apply higher current densities without causing non-uniform plating, as the enclosed volume acts as a buffer.
3Manufacturing precision
If low current density is used to achieve uniform plating and void-free via, then manufacturing precision is maintained, but processing time increases to hours or days
Solution Approach 1:
The plating process is divided into two time segments: a longer first stage at lower current density that establishes uniform plating and enclosed volume, followed by a shorter second stage at higher current density that rapidly completes the filling. This segmentation reduces total processing time while maintaining precision.
Solution Approach 2:
The first plating stage performs the preliminary function of creating uniform metal deposition and the enclosed volume structure. Once this preliminary structure is in place, the second stage can proceed with high current density without sacrificing uniformity, significantly reducing the time loss associated with low current density processing throughout the entire via.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the efficient formation of void-free, conductive through-wafer vias, reducing processing time and ensuring uniform plating, which is crucial for advanced semiconductor packaging and stacked packages.
Implementation Method 1
The conventional fill process is to plate metal into the via
Implementation Method 2
the diffusion of metal ions from a plating solution to the bottom of the via
Data Source
AI summary
A through via is constructed in a two-stage process. A void in a portion of the depth of the substrate is filled from a first surface of the semiconductor substrate creating an enclosed volume within the substrate. Thereafter, the enclosed volume is exposed and the remaining portion of the void is filled.