Two-Stage SAR ADC Sampling Without Signal Division
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Solution Overview
Problem
Conventional analog-to-digital converters (ADCs) face challenges in handling high input voltage ranges without signal division, which leads to a decreased signal-to-noise ratio (SNR) and increased power consumption due to the need for high-voltage transistors and common mode voltage buffering.
Innovation Solution
The proposed solution involves a two-stage ADC system where the first stage samples the input voltage without dividing it, with at least one capacitor left floating, and the second stage makes bit decisions for the floating capacitors, allowing the use of a single-ended supply voltage and reducing power consumption by eliminating the need for common mode voltage buffering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If signal division is used to handle high input voltage ranges, then the input voltage range is extended, but the signal-to-noise ratio decreases
Solution Approach 1:
The ADC is divided into two stages: a first stage that handles the most significant bits by sampling the full input voltage without division, and a second stage that handles the remaining bits. This segmentation allows the system to process high voltage ranges while maintaining high SNR for the critical MSB decisions.
Solution Approach 2:
The first conversion stage performs preliminary conversion of the most significant bits before the second stage processes the remaining bits. By making MSB decisions first on the full-scale voltage, the system establishes the voltage range for subsequent conversion steps, avoiding the need for continuous signal division.
2Adaptability or versatility
If high-voltage transistors are used to handle high input voltages, then the input voltage range is extended, but the power consumption increases
Solution Approach 1:
The conversion process is segmented into two stages with different voltage requirements. The first stage operates on full-scale voltages for MSB decisions, while the second stage operates on reduced voltages for LSB decisions, allowing the use of standard low-voltage transistors for the majority of the conversion process.
Solution Approach 2:
The conversion occurs in periodic phases: first stage conversion for MSBs, then second stage conversion for LSBs. This periodic action allows the system to use high-voltage circuitry only when necessary for brief periods, rather than continuously powering high-voltage transistors.
3Reliability
If common mode voltage buffering is implemented to prevent parasitic diode activation, then the reliability is improved, but the power consumption increases
Solution Approach 1:
The patent extracts and removes the common mode voltage buffering function from the system. By using a single-ended architecture where the negative plate of the sampling capacitor is directly connected to ground, the need for active common mode voltage buffering is eliminated, reducing power consumption while maintaining reliability.
Solution Approach 2:
The ground connection on the negative capacitor plate serves the dual function of providing a stable reference voltage and preventing parasitic diode activation without requiring additional active buffering circuitry. The passive ground connection self-regulates the voltage potential.
4Measurement precision
If the capacitor is continuously connected to reference voltage levels during conversion, then the conversion accuracy is maintained, but the power consumption increases due to continuous switching
Solution Approach 1:
The conversion is segmented into two distinct phases: first stage conversion where the capacitor remains connected to reference voltages for MSB decisions, and second stage conversion where the capacitor is left floating for LSB decisions. This segmentation reduces the total time the switching circuitry must operate at high power levels.
Solution Approach 2:
The capacitor connection state changes periodically: connected during first stage conversion, then left floating during second stage conversion. This periodic action reduces the duty cycle of the switching circuitry, thereby reducing average power consumption while maintaining conversion accuracy through the two-stage approach.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach maintains a high SNR by preserving the full input voltage charge and reduces power consumption by using ground as the supply voltage, minimizing signal division-related losses and parasitic diode activation.
Implementation Method 1
The capacitors C1p and C1n are adapted to evaluate the most significant bit (MSB) and the capacitors CNp and CNn are adapted to evaluate the least significant bit (LSB). The common nodes VCPOS and VCNEG of each of the capacitors C1p-CNp and C1n-CNn can be coupled to a common mode voltage VCM by sample and hold switches SWHp, SWHn.
Implementation Method 2
Successive approximation is one of the basic principles for analog-to-digital conversion. The general functionality and operation of successive approximation register (SAR) analog-to-digital converters (ADCs) is well known in the art. SAR ADCs compare the analog input voltage to reference voltage levels, which can be generated by a digital-to-analog converter (DAC).
Data Source
AI summary
An apparatus for analog-to-digital conversion using successive approximation is provided, which is adapted to be supplied with a single ended supply voltage. The device includes: a first analog-to-digital conversion stage including a first set of capacitors coupled with a side at a common node and adapted to sample an input voltage and to be coupled to either a first reference voltage level or a second reference voltage level, at least one capacitor of the first set of capacitors being adapted to be left floating, a control stage being adapted to connect the at least one floating capacitor to the first reference voltage level or the second reference voltage level in response to an analog-to-digital conversion decision made by a second analog-to-digital conversion stage. The first analog-to-digital conversion stage is operable to couple the common node to a supply voltage level, in particular ground, during analog-to-digital conversion.