Two-Stage Serializer Circuit for Low-Power Chiplet Links
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Solution Overview
Problem
Existing system-on-chip (SOC) devices face challenges in efficiently serializing data between chiplets due to increased power consumption and bandwidth degradation when implementing 4:1 muxes at the transmission driver circuitry.
Innovation Solution
A two-stage data serialization method is introduced, utilizing first multiplexing circuitry to partially serialize a four-bit data group into two-bit subgroups and second multiplexing circuitry with a source-series terminated (SST) driver to serialize these subgroups into a serial data stream based on a delayed quadrature clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If 4:1 muxes are implemented at the transmission driver circuitry, then data serialization is achieved, but power consumption increases
Solution Approach 1:
The patent divides the single 4:1 mux operation into two stages: first a 2:1 mux partially serializes data into 2-bit subgroups, then a second 2:1 mux completes the serialization. This segmentation reduces power consumption by avoiding the high-power single-stage 4:1 mux while achieving the same serialization function.
2Productivity
If 4:1 muxes are implemented at the transmission driver circuitry, then data serialization is achieved, but bandwidth degradation occurs
Solution Approach 1:
By segmenting the serialization into two 2:1 mux stages, the patent maintains better signal integrity and bandwidth compared to a single 4:1 mux stage. The intermediate 2-bit subgroup stage allows for better controlled signal transitions.
Solution Approach 2:
The first 2:1 mux acts as an intermediary stage between the parallel data input and the second 2:1 mux, creating intermediate 2-bit subgroups that are easier to serialize while preserving bandwidth characteristics.
3Measurement precision
If quadrature clock is used for serialization, then timing control is improved, but clock latency must be compensated
Solution Approach 1:
The patent applies preliminary delay to the quadrature clock before it reaches the second 2:1 mux to compensate for the latency introduced by the first 2:1 mux stage. This preliminary timing adjustment ensures proper synchronization without losing data.
Data Source
AI summary
A transmission driver for serial communication includes first multiplexing circuitry configured to partially serialize a data group into data subgroups based on an in-phase clock, and to delay a quadrature clock corresponding to the in-phase clock. The delay is based on latency of the partial serialization. The transmission driver also includes second multiplexing circuitry having a source-series terminated (SST) driver configured to serialize the data subgroups into a serial data stream based on the delayed quadrature clock. The first multiplexing circuitry may be configured to partially serialize the data group into the data subgroups by arranging a four-bit data group into a pair of two-bit data groups, and the second multiplexing circuitry may be configured to serialize the data subgroups into the serial data stream by arranging the pair of two-bit data groups into the serial data stream.