Two-Stage Word Line Decoding Drive Circuit for Smaller DRAM Area
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Solution Overview
Problem
Current DRAM circuit designs for word lines are inefficient, leading to large circuit areas and poor performance due to the need for multiple identical WLDV decoding drivers.
Innovation Solution
A decoding drive circuit with a first-stage and second-stage drive circuit configuration, utilizing switch transistors to generate target word line drive signals, reducing the number of decoding drivers and sharing power supply terminals to improve efficiency and reduce circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple identical WLDV decoding drivers are used to drive word lines, then the word line decoding function is achieved, but the circuit area becomes large and the design becomes complex
Solution Approach 1:
The patent merges multiple identical WLDV decoding drivers into a single shared decoding driver. This single driver generates multiple WLDV signals (WLDV<0> to WLDV<7>) that are shared across different word line groups, eliminating the need for multiple separate decoding drivers and significantly reducing circuit area while maintaining the word line decoding function
Solution Approach 2:
The single WLDV decoding driver is designed to perform multiple functions by generating multiple WLDV signals (WLDV<0> to WLDV<7>) that can decode different word lines (WL<0> to WL<511>). This multi-functional driver replaces what would traditionally require multiple identical drivers, reducing both area and design complexity
2Reliability
If multiple identical WLDV decoding drivers are used to drive word lines, then the word line decoding function is achieved, but the device complexity increases
Solution Approach 1:
The patent combines multiple identical decoding driver circuits into a single integrated decoding driver. This single driver produces multiple WLDV signals that are distributed to different word line groups, reducing the number of decoding driver devices from multiple to one, thereby simplifying the overall device architecture
Solution Approach 2:
The decoding driver is designed as a universal multi-functional device that can decode signals for multiple word lines (WL<0> to WL<511>) through its multiple WLDV outputs (WLDV<0> to WLDV<7>). This multi-functionality eliminates the need for multiple specialized decoding drivers, reducing device complexity
3Reliability
If traditional decoding driver configuration is used, then word line driving is achieved, but the circuit efficiency is poor
Solution Approach 1:
The patent merges multiple decoding driver functions into a single efficient decoding driver that generates multiple WLDV signals. This consolidation improves circuit efficiency by reducing redundant circuitry and optimizing the signal generation process, while still achieving the required word line driving function across multiple memory blocks
Data Source
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AI summary
Embodiments of the disclosure provide a decoding drive circuit and a method therefor, a word line decoding circuit and a semiconductor memory. The decoding drive circuit includes at least one decoding driver. The decoding driver includes a first-stage drive circuit and a second-stage drive circuit. Herein, the first-stage drive circuit is configured to receive an enabling control signal, a decoding input signal and a drive control signal, and generate a first drive signal and a second drive signal according to the enabling control signal, the drive control signal and the decoding input signal. The second-stage drive circuit is configured to generate a target word line drive signal according to the first drive signal and the second drive signal. Thus, the embodiments of the disclosure provide a new decoding drive circuit. The decoding drive circuit performs two-stage amplification on the decoding input signal according to the drive control signal, which can not only improve the circuit efficiency, but also save the circuit area and can improve the performance of a DRAM at the same time.