Two-Step Analog-Digital Converter Reduces Power via Segmented Conversion
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Solution Overview
Problem
Conventional single-slope analog-digital converters in CMOS image sensors consume high power due to the need for high-frequency clock signals to achieve higher bit resolution, leading to increased power consumption.
Innovation Solution
A two-step analog-digital converting circuit that includes a comparator, an upper bit counter, and a pulse residue conversion unit, which compares a ramp signal and an input signal to output upper and lower bit values successively, using a low-frequency clock signal and reducing power consumption by generating voltage proportional to specific time intervals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single-slope ADC uses a high-frequency clock signal to increase converting operation speed and achieve higher bit resolution, then the converting speed and resolution are improved, but power consumption increases
Solution Approach 1:
The patent divides the ADC operation into two distinct steps: a first conversion step that processes the most significant bits (MSBs) and a second conversion step that processes the least significant bits (LSBs). This segmentation allows each step to use optimized clock frequencies - a lower frequency for the MSB conversion and a higher frequency only for the LSB conversion, thereby reducing overall power consumption while maintaining high converting operation speed and resolution
2Measurement precision
If a single-slope ADC increases bit resolution, then measurement precision is improved, but power consumption increases due to requiring higher frequency clock signals
Solution Approach 1:
The patent dynamically adjusts the clock signal frequency based on the conversion step. During the first conversion step for MSBs, a lower clock frequency is used. During the second conversion step for LSBs, a higher clock frequency is applied. This dynamic frequency adjustment enables high bit resolution measurement precision while minimizing power consumption by avoiding sustained high-frequency operation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The two-step analog-digital converting circuit enables fast processing and reduces power consumption by using a low-frequency clock signal, effectively addressing the power consumption issues of conventional ADCs while maintaining high bit resolution.
Implementation Method 1
a voltage generator configured to generate a voltage having a voltage level proportional to a width of the pulse signal in response to the pulse signal
Data Source
AI summary
A two-step analog-digital converting circuit includes a comparator, an upper bit counter and a pulse residue conversion unit. The comparator is configured to compare a ramp signal and an input signal, and to output a resulting comparative signal. The upper bit counter is configured to receive the comparative signal and a clock signal, and to output upper bit values corresponding to a first time interval between a generation time point of the ramp signal and a first edge of the clock signal, the first edge of the clock signal immediately preceding a state transition time point of the comparative signal. The pulse residue conversion unit is configured to receive the comparative signal and the clock signal, and to output lower bit values corresponding to a second time interval between the first edge of the clock signal and the state transition time point of the comparative signal.