Two-Step Capacitor Measurement for MOM Mismatch Correction
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Solution Overview
Problem
High-resolution analog circuits, such as analog-to-digital converters, suffer from metal-oxide-metal (MOM) mismatch due to layout design and process sensitivities, leading to variations in capacitance values across a wafer, which affects measurement precision in low power IoT applications.
Innovation Solution
A two-step charge-based capacitor measurement system using driver circuits with pseudo-inverter transistors and a control circuit to generate independent control signals, allowing for the detection and minimization of MOM mismatch through timing adjustments and shielding metal to reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional capacitor measurement methods are used, then the measurement process is simple, but measurement precision deteriorates due to MOM mismatch and parasitic capacitance
Solution Approach 1:
The measurement process is divided into two distinct steps: first measuring the total capacitance (C_total = C_DUT + C_parasitic), then measuring only the parasitic capacitance (C_parasitic) with the DUT disconnected. This segmentation allows separate measurement of the DUT capacitance by subtraction, eliminating the parasitic error without requiring complex compensation circuits.
Solution Approach 2:
A switch mechanism is introduced as an intermediary to control the connection between the DUT and the measurement circuit. The switch enables selective connection/disconnection of the DUT, allowing the measurement system to first measure with DUT connected, then measure parasitic capacitance alone, and finally calculate the DUT capacitance by difference.
2Ease of manufacture
If layout design is simplified, then manufacturing is easier, but MOM mismatch increases leading to worse measurement precision
Solution Approach 1:
The parasitic capacitance component is extracted and measured separately from the DUT capacitance through the two-step measurement process. By measuring C_parasitic independently and subtracting it from C_total, the method removes the harmful effect of parasitic capacitance without requiring complex layout design or matching techniques.
3Measurement precision
If shielding metal is added to reduce parasitic capacitance, then measurement precision improves, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The parasitic capacitance is measured and characterized in advance (in the second step of the measurement process) before being used to correct the DUT measurement. This preliminary characterization of the parasitic element allows for accurate compensation without requiring physical modification or shielding structures.
Data Source
AI summary
Systems and methods are described herein for charge-based capacitor measurement. The system includes a first pseudo-inverter circuit and a second pseudo-inverter circuit. The system also includes a control circuit coupled between the first inverter circuit and the second inverter circuit. The control circuit is configured to generate independent and non-overlapping control signals for the first pseudo-inverter circuit and the second pseudo-inverter circuit. A shielding metal is coupled to the first pseudo-inverter circuit, the second pseudo-inverter circuit, and the control circuit. The shielding metal is configured to dissipate parasitic capacitance of at least one of the first pseudo-inverter circuit or the second pseudo-inverter circuit. A device under test is coupled to each of the first inverter circuit and the second inverter circuit.