Two-Step Capacitor Measurement with Parasitic Capacitance Shielding
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Solution Overview
Problem
High-resolution analog circuits, such as analog-to-digital converters, suffer from metal-oxide-metal (MOM) mismatch due to layout design and process sensitivities, leading to variations in capacitance values across a wafer, which affects measurement accuracy in low power IoT applications.
Innovation Solution
A two-step charge-based capacitor measurement system using driver circuits with pseudo-inverter transistors and a control circuit to generate independent control signals, allowing for the detection and minimization of MOM mismatch through timing adjustments and shielding metal to reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional capacitor measurement methods are used, then the measurement process is simple, but measurement accuracy deteriorates due to MOM mismatch and parasitic capacitance
Solution Approach 1:
The measurement process is divided into two distinct steps: first measuring the total capacitance (C_total = C_DUT + C_parasitic), then measuring only the parasitic capacitance (C_parasitic) with the DUT disconnected. This segmentation allows separate measurement of the DUT capacitance by subtraction, eliminating the harmful effect of parasitic capacitance on measurement accuracy.
Solution Approach 2:
A control circuit acts as an intermediary between the driver circuits and the DUT, enabling selective connection and disconnection of the DUT from the measurement circuit. This intermediary component facilitates the two-step measurement process by controlling when the DUT is connected (for total capacitance measurement) and when it is disconnected (for parasitic capacitance measurement).
2Ease of manufacture
If layout design is simplified, then manufacturing is easier, but MOM mismatch increases leading to worse measurement accuracy
Solution Approach 1:
The measurement system incorporates feedback by measuring the actual capacitance values including parasitic effects, then using this information to calculate and compensate for MOM mismatch. The system measures C_total and C_parasitic separately, computes the DUT capacitance as C_DUT = C_total - C_parasitic, and can iteratively optimize the layout to minimize mismatch between differential capacitors.
Solution Approach 2:
The system changes the measurement parameters by operating at different connection states (DUT connected vs. disconnected) to extract different capacitance values. This parameter change approach allows the system to work around layout limitations by mathematically eliminating parasitic effects rather than relying solely on perfect symmetry in the physical layout.
3Manufacturing precision
If process sensitivity is reduced, then manufacturing precision improves, but device complexity increases to achieve better control
Solution Approach 1:
The measurement system performs self-characterization by automatically measuring its own parasitic capacitance components and using this information to compensate for process variations. The control circuit autonomously executes the two-step measurement sequence and calculates corrected capacitance values, eliminating the need for external calibration or complex manual compensation procedures.
4Ease of operation
If timing control is relaxed, then operation is easier, but measurement accuracy deteriorates due to signal overlap
Solution Approach 1:
The control circuit uses periodic, non-overlapping clock signals to sequentially activate the driver circuits in a controlled manner. This periodic action ensures that measurements are taken in distinct time windows, preventing signal overlap while maintaining ease of operation through automatic clock-driven sequencing of the measurement steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Improves measurement accuracy by reducing current standard deviation and providing better timing margin control, effectively addressing MOM mismatch and enhancing the precision of capacitor measurements in low power circuits.
Implementation Method 1
two-step charge-based capacitor measurement
Implementation Method 2
shielding metal to reduce parasitic capacitance
Data Source
AI summary
Systems and methods are described herein for charge-based capacitor measurement. The system includes a first pseudo-inverter circuit and a second pseudo-inverter circuit. The system also includes a control circuit coupled between the first inverter circuit and the second inverter circuit. The control circuit is configured to generate independent and non-overlapping control signals for the first pseudo-inverter circuit and the second pseudo-inverter circuit. A shielding metal is coupled to the first pseudo-inverter circuit, the second pseudo-inverter circuit, and the control circuit. The shielding metal is configured to dissipate parasitic capacitance of at least one of the first pseudo-inverter circuit or the second pseudo-inverter circuit. A device under test is coupled to each of the first inverter circuit and the second inverter circuit.