Two-Step CMP Process for Memory Cell Interconnection Planarity
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Solution Overview
Problem
Current memory device fabrication processes face challenges in achieving optimal planarity during chemical-mechanical polishing (CMP) of memory cell structures, leading to issues such as excessive material removal, insufficient material removal, and poor surface topology, which affect the formation of subsequent conductive lines and memory cell arrays.
Innovation Solution
A new process flow that involves forming vertical structures with reduced hard mask thickness and increased top electrode thickness, followed by controlled dry etching to consume the hard mask and optionally the top electrode, and then etching back the dielectric material to expose the top electrode, allowing for improved CMP results and planarity by using a reference level for calibration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a single-step CMP process is used to polish the filling layer, then the process is simple and fast, but it results in poor planarity and excessive or insufficient material removal
Solution Approach 1:
The single-step CMP process is divided into two distinct steps: a first CMP step that removes excess filling material to achieve proper level, and a second CMP step that polishes the surface to achieve high planarity. This segmentation resolves the contradiction by separating the material removal function from the surface polishing function, allowing each step to be optimized independently.
Solution Approach 2:
The first CMP step performs preliminary material removal to establish the correct height level of the filling layer before the second CMP step performs the final polishing. This preliminary action ensures that the subsequent polishing step operates on a properly leveled surface, achieving both adequate material removal and high planarity.
2Manufacturing precision
If CMP is performed on uneven top surfaces of dielectric material, then the process can be simplified, but it results in poor CMP results and defective memory cell arrays
Solution Approach 1:
A planarization layer is formed over the uneven top surfaces of the dielectric material and vertical structures before CMP is performed. This preliminary planarization action creates a uniform surface that enables high-quality CMP processing, preventing defects in the memory cell arrays while adding a controlled level of process complexity.
Solution Approach 2:
The planarization layer acts as an intermediary between the uneven underlying structures and the CMP process. It provides a uniform working surface for CMP while protecting the underlying vertical structures, allowing the CMP process to achieve high precision without directly processing the uneven surfaces.
3Manufacturing precision
If hard mask thickness is reduced and top electrode thickness is increased, then subsequent CMP and etching processes are improved, but the initial structure formation becomes more complex
Solution Approach 1:
The thickness parameters of the hard mask and top electrode are optimized to specific ranges (hard mask: 5-15 nm, top electrode: 20-50 nm) to enable better control during subsequent CMP and etching processes. This parameter optimization improves manufacturing precision by ensuring proper material removal rates and etch selectivity, while the increased top electrode thickness provides a better reference level for CMP calibration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed process flow enhances CMP results by achieving better planarity, improving the formation of conductive lines and subsequent memory cell decks, reducing defects, and ensuring even surface topology, thereby improving the integration and performance of memory cell arrays.
Implementation Method 1
chemical-mechanical polishing (CMP) process
Implementation Method 2
controlled dry etching to consume the hard mask and optionally the top electrode
Data Source
AI summary
Memory cell array architectures and methods of forming the same are provided. An example method for forming an array of memory cells can include forming a plurality of vertical structures each having a switch element in series with a memory element in series with a top electrode, and forming an interconnection conductive material between the respective top electrodes of the plurality of vertical structures. The interconnection conductive material is etched-back and chemical-mechanical polished (CMPed). A conductive line is formed over the interconnection conductive material after CMPing the interconnection conductive material.