Two-Step Single-Slope Comparator for CMOS Sensor Linearity
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Solution Overview
Problem
High-speed operation of CMOS image sensors is limited by the linearity errors and gain errors caused by parasitic capacitors and changing transfer conductance in two-step single-slope analog-to-digital conversion processes.
Innovation Solution
A two-step single-slope comparator is implemented, which includes a first comparison block for sampling a pixel signal and comparing it to a coarse ramping voltage, outputting a residue voltage, and a second comparison block for comparing a fine ramping voltage to the residue voltage, thereby performing analog-to-digital conversion on the residue value.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a two-step analog-to-digital converting device is used to improve operation speed, then operation speed is improved, but linearity error occurs between MSB value and LSB value
Solution Approach 1:
The patent divides the analog-to-digital conversion process into two separate steps: a first comparison block performs MSB conversion by comparing the pixel signal with a coarse ramping voltage, and a second comparison block performs LSB conversion by comparing a fine ramping voltage with the residue voltage. This segmentation allows each block to operate independently with optimized parameters, achieving high-speed conversion while maintaining linearity by eliminating the interaction-induced linearity errors present in integrated single-slope converters.
2Measurement precision
If fine ramping voltage is applied to bottom plate of capacitor, then LSB conversion is enabled, but gain error occurs due to parasitic capacitor
Solution Approach 1:
The patent extracts the fine ramping voltage application from the capacitor bottom plate configuration and implements it through a dedicated second comparison block that directly compares the fine ramping voltage with the residue voltage. This extraction eliminates the parasitic capacitor issues associated with capacitor bottom plate connections, ensuring gain accuracy while enabling precise LSB conversion.
3Adaptability or versatility
If 4-input comparator with four input transistors is used, then conversion capability is enhanced, but linearity error is caused by changed transfer conductance
Solution Approach 1:
The patent segments the comparator functionality into two separate comparison blocks, each with dedicated input transistors optimized for their specific function. The first comparison block uses transistors optimized for coarse ramping and MSB detection, while the second comparison block uses transistors optimized for fine ramping and LSB detection. This segmentation prevents the transfer conductance variations that occur in integrated 4-input comparators, maintaining linearity while preserving full conversion capability.
Data Source
AI summary
A comparator includes a first comparison block suitable for sampling a pixel signal, comparing a sampled pixel signal with a coarse ramping voltage, outputting a first comparison signal, sampling a coarse step voltage and outputting a residue voltage as a difference voltage between the sampled pixel signal and a sampled coarse step voltage; and a second comparison block suitable for comparing a fine ramping voltage with the residue voltage of the first comparison block and outputting a second comparison signal.