Two-Step Feed-Forward Equalizer for Low-Power ISI Mitigation

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Solution Overview

Problem

In high-speed serial links, voltage-mode transmitter architectures face challenges in maintaining energy efficiency and high data rates due to intersymbol interference (ISI) and increased power consumption, particularly when implementing feed-forward equalization, which can degrade I/O bandwidth and circuit layout routing.

Innovation Solution

A two-step feed-forward equalizer is introduced, comprising a coarse and fine equalizer coupled in parallel with calibration circuits to compensate for channel loss, allowing for reconfiguration into multiple segments with adjustable impedance to optimize signal processing and reduce power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If feed-forward equalization is implemented in voltage-mode transmitter architecture, then signal quality and data rate are improved, but power consumption increases

Engineering Contradiction:
Improvesignal qualityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The equalizer is divided into multiple segments with adjustable impedance values. Each segment processes a portion of the signal, allowing the system to achieve effective equalization while consuming less power by selectively activating only the necessary segments based on channel conditions.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The equalizer implements dynamic impedance adjustment capability, where the impedance of each segment can be reconfigured based on detected channel characteristics. This allows the system to optimize power consumption by adapting to different transmission scenarios rather than operating at fixed high power levels.

Inventive Principle:
Principle #15Dynamics

2Reliability

If feed-forward equalization is implemented, then intersymbol interference is reduced, but I/O bandwidth is degraded

Engineering Contradiction:
Improveintersymbol interference mitigationVSAvoidI/O bandwidth
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

By segmenting the equalizer into multiple sections with different impedance values, the circuit can process signals more efficiently. The segmented architecture reduces the capacitive loading effect on the I/O interfaces, thereby preserving bandwidth while still achieving effective ISI mitigation through the combined effect of all segments.

Inventive Principle:
Principle #1Segmentation

3Reliability

If feed-forward equalization is implemented, then signal integrity is improved, but circuit layout complexity increases

Engineering Contradiction:
Improvesignal integrityVSAvoidcircuit layout
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The segmented equalizer structure with standardized impedance values simplifies the circuit layout by creating modular, repeatable units. Each segment can be designed once and then replicated with consistent spacing and routing, reducing overall layout complexity compared to a fully custom distributed equalizer design.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

By establishing standardized impedance values for each segment, the design transforms a complex continuous optimization problem into a discrete parameter selection problem. This allows for simpler layout rules and easier integration with standard fabrication processes.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10728060B2Two-step feed-forward equalizer for voltage-mode transmitter architecture
Publication Date: 2020.07.28 TELETRX CO
  • US10728060B2 patent drawing
  • US10728060B2 patent drawing
  • US10728060B2 patent drawing

AI summary

A driver for a transmitter includes an output stage comprising a first equalizer and a second equalizer, coupled to an output circuit of the transmitter, being operable for receiving a plurality of differential input data streams to generate an equalized differential output signals, wherein the first equalizer and the second equalizer being coupled and reconfigured to form a plurality of parallel driver segments, each driver segment having a calibration circuit, at least one of the calibration circuits been enabled to control the impedance of the output circuit, the plurality of differential input data streams are processed by the first and the second equalizer to shape the plurality of differential input data streams for compensating the channel loss.