Two-Step Floating Gate Flash Memory Erase Optimization
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Solution Overview
Problem
Split-gate flash memory devices require longer times for erasing operations due to the inefficiency of Fowler-Nordheim tunneling, which affects the overall performance and efficiency of the memory device.
Innovation Solution
The method involves creating a silicon substrate structure with a two-step floating gate design, where the dimensions and thicknesses of the step structures are configured to minimize voltage requirements for Fowler-Nordheim tunneling and facilitate the flow of hot electrons into the erase gate, optimizing erasing efficiency without compromising other performance characteristics like erase state read current and data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Fowler-Nordheim tunneling is used for erasing operation in split-gate flash memory device, then electrons can be removed from floating gate, but the erasing operation requires substantially longer time than programming operation
Solution Approach 1:
The floating gate is segmented into two distinct levels (first floating gate and second floating gate) positioned at different heights. This segmentation allows independent control and optimization of electron removal paths for each level, enabling faster overall erasing by simultaneously processing electrons from both levels through dedicated tunneling paths.
Solution Approach 2:
The invention introduces a vertical dimension to the floating gate structure by creating a two-level stacked configuration. The first floating gate is positioned at a lower level while the second floating gate is positioned at a higher level, both above the control gate. This dimensional change creates separate tunneling paths with different oxide thicknesses, allowing optimized electron transport for each level and significantly reducing total erasing time.
2Reliability
If high negative bias is applied to control gate for Fowler-Nordheim tunneling, then electrons can travel through sidewall oxide layer into erase gate, but the process is inefficient and time-consuming
Solution Approach 1:
Different oxide layer thicknesses are applied to different regions: a first sidewall oxide layer with greater thickness protects the first floating gate, while a second sidewall oxide layer with lesser thickness enables efficient electron removal from the second floating gate. This localized differentiation of oxide properties allows optimized electron transport for each floating gate level, improving overall erasing efficiency without compromising data retention.
Solution Approach 2:
The invention changes the oxide layer thickness parameter to optimize electron transport. By making the second sidewall oxide layer thinner than the first sidewall oxide layer, the tunneling barrier for the second floating gate is reduced, enabling faster electron removal during erasing operations while maintaining adequate protection for the first floating gate through its thicker oxide layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The two-step floating gate structure enhances the efficiency of erasing operations in flash memory devices while maintaining satisfactory performance across other characteristics, thereby optimizing the memory device's performance without increasing voltage requirements.
Implementation Method 1
a high negative bias may be applied to the control gate, such that hot electrons in the floating gate may take advantage of Fowler-Nordheim tunneling to travel through a sidewall oxide layer into the erase gate (EG)
Implementation Method 2
a high positive bias may be applied to the control gate (CG), such that hot electrons may be injected from the source through an oxide layer into the floating gate (FG)
Data Source
AI summary
A method for manufacturing a memory device may include obtaining a substrate structure that includes a substrate, an oxide material layer positioned on the substrate, a polysilicon material layer positioned on the oxide material layer, a first control gate and a second control gate positioned on the polysilicon material layer, and an offset oxide layer positioned between the first control gate and the second control gate. The method may further include the following steps: removing, using the offset oxide layer as a first mask, a portion of the polysilicon material layer for forming a polysilicon structure that includes a first step structure; forming a masking oxide layer on the offset oxide layer; removing, using the masking oxide layer as a second mask, a portion of the polysilicon structure for forming a floating gate polysilicon member that includes the first step structure and a second step structure.