Two-Step Metal Patterning for Organic EL Display Yield
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Solution Overview
Problem
The high pattern density in organic EL display devices makes them prone to yield reduction due to etching residue from foreign matters, leading to pattern collapse and increased parasitic capacitance, which results in display unevenness.
Innovation Solution
A method involving a two-step patterning process where a first resist pattern is used for initial etching and a second resist pattern with a smaller shape is used for rework, preventing line width increase and maintaining parasitic capacitance, thereby improving yield and preventing display unevenness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a rework process with the same line width is performed to remove etching residue, then the short-circuit defect is eliminated, but the wiring line width becomes too small compared with design dimensions due to misalignment
Solution Approach 1:
The patent applies local quality by making the second resist pattern have a larger line width than the first resist pattern. This local modification allows the rework process to compensate for misalignment and remove etching residue effectively, while the larger line width provides a margin of error that prevents the final wiring line from becoming too narrow. The second resist pattern is specifically designed with different dimensions (larger by approximately 1.5 μm) to address the local problem of etching residue removal without compromising the overall wiring line width accuracy.
2Manufacturing precision
If the second resist pattern has a larger line width to compensate for misalignment, then the wiring line width accuracy is maintained, but the interval between adjacent wiring lines decreases, leading to increased parasitic capacitance
Solution Approach 1:
The patent applies partial or excessive action by making the second resist pattern larger than necessary for the final wiring line width. The second resist pattern is intentionally oversized (larger by approximately 1.5 μm) to provide a margin that accommodates misalignment during the rework process. This excessive sizing ensures that even with misalignment, the etching residue can be removed while maintaining the correct final wiring line width, and the larger resist pattern helps maintain proper spacing between wiring lines to control parasitic capacitance.
3Ease of manufacture
If a single etching step is performed to pattern the metal film, then the manufacturing process is simple, but etching residue from foreign matters causes pattern collapse and yield reduction
Solution Approach 1:
The patent applies segmentation by dividing the single patterning process into two separate etching steps: a first etching step using a first resist pattern, and a second etching step using a second resist pattern. This segmentation allows the process to address foreign matter contamination effectively. The first etching step performs the initial patterning, and the second etching step serves as a rework step that removes etching residue caused by foreign matters. This two-step approach segments the defect removal function from the main patterning function, improving yield without significantly complicating the overall manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reworks pattern collapse without increasing wiring line width, maintaining parasitic capacitance and enhancing the yield of organic EL display devices by preventing short-circuits and line defects.
Implementation Method 1
a patterning step of forming a metal film on the substrate and patterning the metal film. Patterning of the metal film is performed by etching in which a resist film formed on the metal film is exposed and developed by photolithography
Data Source
AI summary
A method for manufacturing a display device includes a pixel circuit formed on a substrate, wherein a manufacturing process of the pixel circuit includes a patterning step of a metal film performed in the following procedures (a) to (e): (a) forming the metal film on the substrate; (b) forming a first resist pattern on the metal film by a photolithographic method; (c) etching the metal film with the first resist pattern to form a first metal pattern; (d) forming by the photolithographic method on the metal film formed in the first metal pattern, a second resist pattern including a pattern shape smaller than a pattern shape of the first resist pattern; and (e) etching the metal film with the second resist pattern to form a second metal pattern.