Two-Step Photolithography for Short Gate Length Transistors
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Solution Overview
Problem
Conventional electron beam lithography for fabricating III-V transistors with short gate lengths is costly and time-consuming, making it unsuitable for mass production due to its limitations in forming minimum line widths and high operational costs.
Innovation Solution
A two-step photolithography method is employed to form transistors with short gate lengths by creating overlapping openings in a passivation layer, allowing for adjustable gate length control through the overlapping width of the openings, which can be achieved using a stepper to increase manufacturing efficiency and reduce costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional electron beam lithography is used to fabricate III-V transistors with short gate lengths, then high precision gate length control can be achieved, but the manufacturing cost increases and production time is excessive
Solution Approach 1:
The patent divides the gate formation process into two separate photolithography steps: first forming a mandrel structure, then forming a gate electrode structure that overlaps with the mandrel. This segmentation allows each step to be optimized independently and enables parallel processing, thereby improving production efficiency while maintaining precision through the overlapping width control
Solution Approach 2:
The patent introduces a mandrel structure as an intermediary element that mediates between the photolithography process and the final gate formation. The mandrel serves as a template that defines the overlapping region, enabling precise gate length control through the overlapping width between the mandrel and gate electrode, while allowing standard photolithography equipment to achieve results previously requiring electron beam lithography
2Manufacturing precision
If conventional electron beam lithography is used to fabricate III-V transistors with short gate lengths, then high precision gate length control can be achieved, but the manufacturing cost increases
Solution Approach 1:
The patent uses a disposable mandrel structure that is formed through standard photolithography and then removed after serving its purpose as a template. This approach replaces expensive electron beam lithography with cheaper, standard photolithography equipment, significantly reducing manufacturing costs while maintaining precision through the controlled overlapping width
Solution Approach 2:
The mandrel acts as a temporary intermediary that enables precise pattern transfer using standard photolithography equipment. By using this intermediary structure, the patent achieves electron beam lithography-level precision with much lower cost equipment, making the process economically viable for mass production
3Productivity
If two-step photolithography is used to form overlapping openings for short gate lengths, then manufacturing efficiency and cost are reduced, but the process complexity increases
Solution Approach 1:
The patent uses standard photolithography equipment for both the mandrel formation and gate electrode formation steps, making the equipment serve multiple functions. This universal use of standard equipment improves manufacturing efficiency and reduces cost, while the added process steps are offset by eliminating the need for specialized electron beam lithography equipment
Solution Approach 2:
The patent performs preliminary action by forming the mandrel structure first, which serves as a pre-defined template for the subsequent gate electrode formation. This preliminary mandrel creation enables precise overlapping width control and simplifies the second photolithography step, as the mandrel already defines the critical dimensions before the gate material is deposited
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the production of transistors with gate lengths as short as 0.05-0.25 μm, suitable for high electron mobility transistors like GaN and GaAs, improving manufacturing efficiency and reducing costs while maintaining high precision.
Implementation Method 1
The first photoresist layer is patterned by a first photolithography to expose a portion of the passivation layer
Implementation Method 2
The metal layer on the second photoresist layer is lifted-off to form a gate of the transistor in the second opening
Data Source
AI summary
A method of fabricating transistors with short gate length by two-step photolithography is provided. This method utilizes the two-step photolithography by a stepper as well as controlling a first exposed position and a second exposed position to change the gate length.