Two-Step Pixel ADC for High Dynamic Range With Lower Noise
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Solution Overview
Problem
Current ROIC technology faces challenges in achieving large charge capacity with small pixel pitch due to increased transistor noise and power dissipation, especially in large format mega-pixel focal plane arrays, where analog circuits do not scale well and in-pixel ADCs introduce noise and high costs.
Innovation Solution
A low power two-step ADC circuit with a dual function comparator, step charge subtractor, state latch, coarse N-bit counter, and residue signal M-bit time-to-digital converter, which reduces charge reset noise and transistor count, allowing for efficient analog-to-digital conversion with reduced pixel size and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If in-pixel ADC is implemented to increase digital resolution, then measurement precision is improved, but device complexity and power dissipation increase significantly
Solution Approach 1:
The patent divides the 14-bit ADC into two segments: an 11-bit in-pixel ADC that counts charge packets during integration, and a 3-bit post-integration ADC that digitizes the residual voltage on CINT. This segmentation allows high-resolution conversion without requiring a full 14-bit counter in each pixel, reducing pixel complexity while maintaining overall digital resolution.
Solution Approach 2:
The patent moves part of the ADC functionality from the spatial dimension (in-pixel) to the temporal dimension (post-integration). By performing initial digitization during integration and completing the conversion after integration using the residual signal, the system achieves high resolution without requiring all ADC components to be present simultaneously in each pixel.
2Area of moving object
If pixel pitch is reduced to increase array density, then area is reduced, but transistor noise increases and analog circuit performance deteriorates
Solution Approach 1:
The patent replaces traditional analog charge-to-voltage conversion with a hybrid approach that uses in-pixel charge packet counting. This substitution reduces reliance on analog circuits (which are noisy at small scales) while maintaining charge integration functionality, thereby reducing transistor noise in scaled pixels.
Solution Approach 2:
The patent changes the operating parameters of the pixel by using voltage reset instead of charge reset for CINT. This parameter change reduces the noise contribution from the reset process and allows the circuit to function effectively at smaller geometries where analog performance is degraded.
3Measurement precision
If charge reset is used to reset CINT, then measurement precision is improved, but reset noise increases
Solution Approach 1:
The patent extracts the reset noise problem from the charge reset process by implementing voltage reset instead. By resetting the integration node voltage rather than injecting charge, the system maintains charge counting accuracy while eliminating the kTC noise associated with charge reset capacitors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively converts analog signals to digital signals with reduced noise and power consumption, enabling high-resolution imaging in large format arrays with improved dynamic range and signal-to-noise ratio, while minimizing the impact of transistor noise and increasing the feasibility of large format mega-pixel FPAs.
Implementation Method 1
an integration capacitor CINT connected in parallel to the integration node
Implementation Method 2
a comparator having a first input connected to the integration node and a second input connected to a reference voltage VCMP
Data Source
AI summary
In one or more embodiments, an apparatus and method for processing an analog signal into a digital signal includes an input current buffer circuit, a signal charge integration node, a dual function comparator, a step charge subtractor, a state latch, a coarse N-bit counter, an optional residue signal buffer and a residue signal M-bit time-to-digital (TDC) converter. The circuitry is free running, meaning that it is never reset. Instead, what is tracked for each frame is how much additional charge has been accumulated since the end of the previous integration period. Between each frame, the state of the counter and the amount of charge residing in the integration node are recorded. This information from the beginning and end of a given frame is differenced and to this is added the amount of charge indicated by the number of times the counter overflowed during the integration period.