Two-Step Shallow Trench Isolation for MOS Stress Reduction
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Solution Overview
Problem
The formation of shallow trench isolation (STI) regions in integrated circuits generates stresses and dopant concentration fluctuations due to thermal expansion differences and voids, affecting the performance of metal-oxide-semiconductor (MOS) devices, particularly in the gate length direction.
Innovation Solution
A two-step method of forming STI regions, where the first STI region is created before MOS device formation, followed by a second STI region formed after MOS device construction, including etching a trench and filling it with inter-layer dielectric to reduce stress and dopant fluctuations, with the second STI region having a top surface higher than the gate electrode strips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If STI regions are formed before MOS device formation, then isolation structures are established early in the process, but stresses are generated during high-temperature process steps affecting MOS device performance
Solution Approach 1:
The STI formation process is divided into two separate steps: first STI regions are formed before MOS device formation, and second STI regions are formed after MOS device formation. This segmentation allows the process to benefit from early isolation structure establishment while avoiding stress-induced performance degradation by completing critical STI formation after high-temperature processing is complete.
Solution Approach 2:
The first STI regions are formed preliminarily before MOS device formation to establish isolation structures early in the manufacturing process, providing structural foundation and isolation for subsequent device fabrication steps.
2Ease of manufacture
If STI regions are formed before MOS device formation, then isolation structures are established early, but dopant diffusion into STI regions causes concentration fluctuations in active regions
Solution Approach 1:
The STI formation is segmented into first and second steps, with the critical dopant implantation and activation steps occurring between them. This prevents dopant diffusion into STI regions during high-temperature processing, maintaining uniform dopant concentrations in active regions while still establishing isolation structures early through the first STI formation.
3Reliability
If the width of STI strips is increased, then isolation effectiveness is improved, but voids are more likely to be generated in STI regions
Solution Approach 1:
Different STI regions are formed with different widths and characteristics: first STI regions have larger widths for effective isolation, while second STI regions are formed with controlled dimensions after MOS device formation. This local differentiation allows each STI region to be optimized for its specific function, maintaining isolation effectiveness while avoiding void formation in critical areas.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces undesirable stresses on MOS devices and improves their performance by minimizing adverse effects from thermal expansion and dopant diffusion, while avoiding voids in the STI regions.
Implementation Method 1
forming an inter-layer dielectric (ILD) over the MOS device, wherein the ILD extends into the trench to form a second STI region
Implementation Method 2
stresses are generated due to the different coefficients of thermal expansion between STI regions 8 and active regions 6 and 16
Implementation Method 3
In the portions of active regions 6 and 16 near STI regions 8, dopant concentrations may have fluctuations due to the diffusion of the dopants into STI regions 8
Data Source
AI summary
A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming a first isolation region in the semiconductor substrate; after the step of forming the first isolation region, forming a metal-oxide-semiconductor (MOS) device at a surface of the semiconductor substrate, wherein the step of forming the MOS device comprises forming a source/drain region; and after the step of forming the MOS device, forming a second isolation region in the semiconductor substrate.