Two-Step Plasma Etching for Via Formation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional plasma etching methods for forming vias in semiconductor manufacturing face challenges such as un-landing vias causing micro-trenches, residue deposition, and increased destructibility of conductive structures due to precision and electric property issues, particularly in high-density integrated circuit fabrication.
Innovation Solution
A two-step plasma etching method using distinct etching mixtures with varying flow rates and pressures to control etching rates and polymer deposition, ensuring precise via formation with reduced sidewall exposure and enhanced residue removal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional plasma etching method is used to form via, then via depth can be controlled, but un-landing via is formed causing micro-trench and residue deposition
Solution Approach 1:
The patent divides the via formation process into two separate etching steps: a first etching step to form a via through the mandrel layer, and a second etching step to form a via through the dielectric layer. This segmentation allows each step to be optimized independently, preventing un-landing via and micro-trench formation while enabling complete residue removal between steps.
Solution Approach 2:
The patent performs the first etching step through the mandrel layer before performing the second etching step through the dielectric layer. This preliminary action creates a foundation structure that guides the subsequent etching process, ensuring proper via formation and preventing harmful micro-trench effects.
2Manufacturing precision
If etching parameters are set for desired via depth, then via depth is achieved, but conductive structure sidewall exposure increases causing damage
Solution Approach 1:
The patent segments the etching process into two distinct steps with different etching mixtures and parameters. The first step uses a first etching mixture optimized for mandrel layer etching, while the second step uses a second etching mixture optimized for dielectric layer etching. This segmentation allows control of sidewall exposure in each step independently, preventing conductive structure damage while achieving desired via depth.
Solution Approach 2:
The patent changes etching parameters between the two steps by using different etching mixtures. The first etching mixture has parameters optimized for etching through the mandrel layer, while the second etching mixture has parameters optimized for etching through the dielectric layer with reduced sidewall exposure. This parameter change allows precise control of via depth while minimizing damage to conductive structures.
3Device complexity
If single etching step is used, then process simplicity is maintained, but via formation precision and residue removal are insufficient
Solution Approach 1:
The patent divides the via formation into two sequential etching steps performed by the same plasma etching device. The first step etches through the mandrel layer, and the second step etches through the dielectric layer. This segmentation improves via formation precision and enables complete residue removal between steps, while maintaining process simplicity by using the same equipment throughout.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method achieves precise via formation with reduced sidewall exposure, minimizing damage to conductive structures and facilitating easy residue removal, thereby improving electric properties and avoiding dead spaces in semiconductor devices.
Implementation Method 1
By using the physical attacking and chemical etching effects, controlled by plasma conditions and gas chemical compounds
Implementation Method 2
By using the physical attacking and chemical etching effects, controlled by plasma conditions and gas chemical compounds
Implementation Method 3
The high selective ratio is achieved due to chemical reaction. Re-deposited production or polymer is formed on the expected etched pattern
Implementation Method 4
A portion of the deposition, formed on the surface of the pattern, is continuously removed by ions, and thus etched
Data Source
AI summary
The invention provides a method for forming a via. A first dielectric layer is formed on a substrate. A conductive structure is formed in the first dielectric layer. A second dielectric layer is formed on the first dielectric layer and conductive structure. A first etching step is performed by using a first etching mixture to form a first via in the second dielectric layer. A second etching step is performed by using a second etching mixture to form a second via under the first via. The second via exposes at least a top surface of the conductive structure. An etching rate of the second etching step is slower than the first etching step.