Two-Step Via Structure for Low-Resistance Semiconductor Interconnects

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Via resistance increases as via bottom widths are made smaller in advanced technology nodes, and there is a challenge in maintaining effective metal filling and reducing bridging in conductive layers of semiconductor devices.

Innovation Solution

Implementing two-step via structures with increased via widths to reduce via resistance and improve metal filling, while maintaining small contact areas to prevent bridging.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If via bottom widths are made smaller to scale down devices, then device density increases, but via resistance increases

Engineering Contradiction:

Improvedevice densityVSAvoidvia resistance

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The via structure is divided into multiple segments with different widths: a narrower bottom portion for high density and a wider top portion for low resistance. This segmentation allows the via to simultaneously achieve both high device density and low via resistance by having different width characteristics in different vertical zones.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different portions of the via structure are given different local qualities (widths) to optimize for different functions. The bottom portion has a narrower width optimized for density, while the top portion has a wider width optimized for reducing resistance, allowing each local region to perform its specific function effectively.

Inventive Principle:

Principle #3Local quality

2Reliability

If via widths are increased to reduce via resistance, then via resistance decreases, but contact area increases causing bridging

Engineering Contradiction:

Improvevia resistanceVSAvoidbridging

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The via structure is segmented vertically with a narrow bottom section that maintains small contact area to prevent bridging, and a wide top section that reduces via resistance. This segmentation resolves the contradiction by assigning different width characteristics to different vertical zones of the same via.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The solution moves from a single uniform width parameter to a two-dimensional width profile (narrow at bottom, wide at top). By utilizing the vertical dimension to create a gradient width structure, the patent simultaneously achieves low resistance (through the wide top portion) and prevents bridging (through the narrow bottom portion).

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20250343142A1Semiconductor device and method of forming thereof

Publication Date: 2025.11.06 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A method includes forming a first etch stop layer (ESL) over a conductive feature, forming a first dielectric layer on the first ESL, forming a second ESL on the first dielectric layer, forming a second dielectric layer on the second ESL, forming a trench in the second dielectric layer, forming a first opening in a bottom surface of the trench extending through the second dielectric layer, and forming a second opening in a bottom surface of the first opening. The second opening extends through the first dielectric layer and the first ESL. The second opening exposes a top surface of the conductive feature. The method further includes widening the first opening to a second width, filling the trench with a conductive material to form a conductive line, and filling the second opening and the first opening with the conductive material to form a conductive via.