Two-Tap Unrolled DFE Circuit for High-Speed ISI Recovery
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Solution Overview
Problem
High-speed serial communication systems face challenges in recovering transmitted signals due to interference and attenuation, leading to intersymbol interference (ISI), which conventional decision feedback equalizers (DFE) struggle to address efficiently, especially at high data rates, as the addition of taps increases power consumption and hardware complexity.
Innovation Solution
Implementing a two-tap unrolled DFE circuit that applies parallel corrections using a clock recovery circuit, where the first correction is fully applied with both positive and negative polarities, and the second correction is partially applied with either positive or negative polarity, allowing for hardware components of a single tap unrolled DFE, reducing physical area, material, and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple tap values are added to increase recovery accuracy, then signal recovery accuracy is improved, but timing delay and hardware cost increase
Solution Approach 1:
The patent segments the DFE circuit into multiple independent unrolled paths (first unrolled DFE circuit, second unrolled DFE circuit, etc.), where each path processes a different subset of tap values. This segmentation allows parallel processing of multiple tap corrections without requiring a single complex sequential circuit, thereby improving signal recovery accuracy while controlling hardware complexity through modular design
Solution Approach 2:
The patent introduces a new dimension of parallel processing by implementing multiple unrolled DFE circuits that operate simultaneously on different data streams or tap combinations. This dimensional expansion from sequential to parallel architecture enables the system to handle multiple tap corrections concurrently, achieving higher accuracy without proportionally increasing timing delay
2Measurement precision
If multiple tap values are added to increase recovery accuracy, then signal recovery accuracy is improved, but timing delay increases
Solution Approach 1:
The patent pre-calculates and stores tap correction values in lookup tables or registers before they are needed during the equalization process. By preparing correction values in advance and making them readily available, the circuit avoids computation delays during critical signal processing, thereby maintaining high accuracy while minimizing timing delay
Solution Approach 2:
The patent implements continuous parallel processing through multiple unrolled DFE circuits that operate simultaneously and continuously. This eliminates idle time and ensures that correction operations are performed without interruption or sequential waiting, maintaining both high accuracy and minimal timing delay through uninterrupted parallel execution
3Reliability
If conventional DFE is used to correct current symbol, then ISI cancellation is achieved, but power consumption and hardware area increase at high data rates
Solution Approach 1:
The patent extracts and implements only the essential second tap correction functionality in dedicated unrolled circuits, rather than implementing a full conventional DFE with all taps. By taking out and selectively implementing only the most critical correction taps in simplified unrolled architectures, the system achieves effective ISI cancellation while significantly reducing power consumption and hardware area
Solution Approach 2:
The patent employs simplified unrolled DFE circuit structures that use less complex, lower-power components compared to conventional DFE implementations. These streamlined circuits use basic logic elements and simple arithmetic operations instead of complex adaptive algorithms, achieving adequate ISI cancellation with reduced power consumption suitable for high-speed serial communication
Data Source
AI summary
Various embodiments provide a method or system that implements a two-tap decision feedback equalizer by applying a first tap and a second tap on a first symbol of a data signal, each of the first and second taps having a first and second polarity to generate a first corrected data symbol and a second corrected data symbol. The first corrected data symbol and the second corrected data symbol is provided to a comparator to select a data symbol. The output of the comparator is provided to a clock data recovery circuit along with a previous data symbol of the data signal preceding the first data symbol.