Two-Terminal Memory Emulating NAND Operations
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Solution Overview
Problem
NAND flash memory technologies face limitations such as high bit error rates, low program/erase cycle count, slow read speeds, and increased overhead due to architectural constraints, which affect memory reliability and performance, particularly at smaller technology nodes.
Innovation Solution
The development of two-terminal memory devices that can be programmed to emulate NAND-based memory operations, allowing for direct overwrite and erase operations without block-level erasure, reducing write amplification and enhancing memory endurance and access times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If NAND flash memory is used, then storage capacity and non-volatility are achieved, but read speed is slow and access time is increased
Solution Approach 1:
The patent changes the fundamental operating parameters of the memory device by transitioning from three-terminal NAND flash architecture to two-terminal resistive switching memory architecture. This architectural parameter change enables direct read access without the complex charge tunneling processes of NAND flash, achieving read speeds up to 100x faster while maintaining non-volatile storage capabilities.
Solution Approach 2:
The patent replaces the mechanical/electrical charge storage mechanism of NAND flash with an electrical resistance-based memory mechanism. The resistive switching memory uses filament formation and rupture in oxide materials to store data, eliminating the need for charge tunneling through floating gates, thereby achieving faster read speeds and reduced access times.
2Quantity of substance
If NAND flash memory operates at smaller technology nodes, then storage density increases, but bit error rate increases and reliability decreases
Solution Approach 1:
The patent employs composite material structures in the resistive switching memory, combining metal layers (such as tungsten or copper) with oxide materials (such as silicon oxide or hafnium oxide) to form filament-forming composite structures. This composite approach enables stable resistance states and reliable switching behavior even at scaled dimensions, maintaining low bit error rates while achieving high storage density.
Solution Approach 2:
The patent changes the physical mechanism of data storage from charge-based to resistance-based, which fundamentally alters how data is read and written. The resistance-based mechanism is less susceptible to the variability and error mechanisms that plague scaled NAND flash, thereby maintaining reliability at smaller technology nodes while achieving high density through vertical stacking and crossbar architectures.
3Duration of action of moving object
If NAND flash memory performs program/erase operations, then data storage is achieved, but program/erase cycle count is limited and endurance is reduced
Solution Approach 1:
The patent replaces the program/erase mechanism of NAND flash with a resistive switching mechanism that forms or ruptures conductive filaments in oxide materials. This mechanism does not involve charge tunneling or floating gate modification, which are the limiting factors for program/erase cycles in NAND flash. The resistive switching mechanism can endure billions of cycles with minimal degradation, dramatically improving memory endurance.
Solution Approach 2:
The patent changes the operational parameters from charge injection/extraction to resistance switching through filament formation/rupture. This parameter change enables symmetric read/write operations without the need for erase-before-write sequences, allowing direct overwrite operations and eliminating write amplification, thereby achieving near-limitless program/erase cycle counts.
4Adaptability or versatility
If NAND flash memory emulates traditional memory operations, then compatibility is maintained, but overhead increases and efficiency is reduced
Solution Approach 1:
The patent creates a universal memory interface that can operate in multiple modes: NAND flash emulation mode for compatibility with existing controllers and protocols, and native two-terminal memory mode for optimized performance. This multi-functionality allows the same hardware platform to serve both legacy compatibility needs and next-generation performance requirements without sacrificing either.
Solution Approach 2:
The patent extracts the essential functionality of NAND flash operation (read, write, erase capabilities) and implements it through a simpler two-terminal resistive switching mechanism. By taking out the complex three-terminal architecture and charge management requirements, the design achieves NAND compatibility through software/firmware emulation while eliminating the physical overhead and complexity of the original NAND architecture.
Data Source
AI summary
Operating characteristics associated with non-volatile two-terminal memory can be modified post-fabrication, e.g., by a controller that controls the non-volatile two-terminal memory. As a result, two-terminal memory arrays included in memory devices (e.g., memory cards, solid-state drives, etc.) can be flexibly modified to provide numerous advantages over other types of non-volatile memory.