Two-Tier NoC Routing for Uniform Memory Controller Access
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Solution Overview
Problem
Modern integrated circuits face challenges in efficiently managing large data movements with reduced latency and uniform memory access, as existing network-on-chip (NoC) structures do not fully meet the requirements for low latency and high-bandwidth memory connections.
Innovation Solution
Implementing a NoC with a sparse network coupled to processing elements and a non-blocking network coupled to memory controllers, allowing for deterministic memory access performance and efficient re-mapping of applications and memory associations without changing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a traditional NoC structure is used for data movement, then connectivity between processing elements and memory controllers is provided, but latency is increased and memory access uniformity is not achieved
Solution Approach 1:
The NoC is segmented into a two-tier architecture: a sparse network tier for basic connectivity and a non-blocking network tier for high-performance memory access. This segmentation allows different parts of the network to be optimized for different functions, reducing overall latency while maintaining manageable complexity through modular design.
Solution Approach 2:
The non-blocking network acts as an intermediary layer between the sparse network and memory controllers. It mediates memory access requests by providing dedicated high-speed paths that bypass the congestion and variability of the sparse network, ensuring uniform and low-latency access to memory controllers.
2Productivity
If applications are re-mapped to different processing elements, then utilization of processing elements and memory is improved, but memory access performance may vary
Solution Approach 1:
The non-blocking network provides universal access capabilities that work consistently regardless of which processing element an application is mapped to. Any processing element can access any memory controller through the non-blocking network with the same performance characteristics, enabling flexible re-mapping while maintaining performance consistency.
Solution Approach 2:
The system changes the network path parameters dynamically based on application location. When an application is re-mapped to a different processing element, the non-blocking network adjusts the access paths to maintain uniform latency and bandwidth characteristics, ensuring performance parameters remain consistent across different mappings.
3Quantity of substance
If high-bandwidth memory connections are implemented, then data movement capacity is increased, but latency and access uniformity requirements are not met
Solution Approach 1:
The non-blocking network provides locally optimized high-bandwidth connections between processing elements and memory controllers with deterministic low latency. Different regions of the network have different quality characteristics: the sparse network provides general connectivity while the non-blocking network provides high-quality, low-latency paths for memory access, allowing both bandwidth and latency requirements to be met simultaneously.
Data Source
AI summary
An integrated circuit device includes a processing element, a plurality of memory controllers, and a network on chip (NoC). The NoC has a first network including a plurality of interconnected switches having routing tables and a second network coupled to the first network. The second network includes a crossbar. The NoC is configured to implement a path coupling the processing element and the plurality of memory controllers in which a first portion of the path is implemented in the first network and a second portion of the path is implemented in the second network. The crossbar connects the processing element to any memory controller of the plurality of memory controllers while maintaining a same delay for the path.