Two-Track Cross-Connect in Double-Patterned ICs
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Solution Overview
Problem
Integrated circuits face challenges in forming desired metal interconnect layouts and crossovers with existing photolithography processes, particularly at technology nodes beyond 28 nanometers, where achieving the right tradeoffs between fabrication costs and yield is difficult, and forming crossovers between adjacent parallel route tracks with desired lateral dimensions is problematic.
Innovation Solution
A process involving the formation of first and second interconnect patterns in alternating parallel route tracks, with a stretch crossconnect formed in a vertical connecting level to electrically connect leads, which is not connected to other interconnect elements, allowing for concurrent formation with other vertical interconnects, thereby reducing the integrated circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithography processes are used to form metal interconnect layouts, then fabrication costs are controlled, but manufacturing precision deteriorates at technology nodes beyond 28 nanometers
Solution Approach 1:
The patent divides the formation of metal interconnect layouts into multiple sequential lithography steps (e.g., self-aligned double patterning, self-aligned quadruple patterning) rather than attempting to form the complete layout in a single exposure step. This segmentation allows each step to work within the resolution capabilities of 193nm illumination sources while achieving finer final feature sizes through cumulative pattern refinement.
Solution Approach 2:
The patent employs preliminary patterning steps that create intermediate structures (such as mandrels, spacers, or sacrificial layers) before forming the final metal interconnect pattern. These preliminary structures are formed with relaxed dimensional requirements using conventional lithography, then used as templates to guide subsequent steps that achieve the required nanometer-scale precision.
2Reliability
If conventional crossover structures are formed between adjacent parallel route tracks, then electrical connectivity is achieved, but area usage increases due to larger lateral dimensions
Solution Approach 1:
The patent transitions from planar crossover structures to three-dimensional vertical crossovers by forming conductive vias and contacts that extend through multiple interconnect layers. This dimensional change allows adjacent parallel route tracks to cross without increasing lateral footprint, as the connectivity is achieved through the vertical dimension rather than requiring large lateral overlap areas in the same plane.
Solution Approach 2:
The patent implements nested interconnect structures where conductive elements in upper layers are positioned within or adjacent to vias/contacts in lower layers, creating a hierarchical nesting pattern. This allows multiple routing layers to share vertical space efficiently, reducing the overall lateral area required for crossovers while maintaining reliable electrical connections through each layer.
Data Source
AI summary
An integrated circuit may be formed by forming a first interconnect pattern in a first plurality of parallel route tracks, and forming a second interconnect pattern in a second plurality of parallel route tracks, in which the second plurality of route tracks are alternated with the first plurality of route tracks. The first interconnect pattern includes a first lead pattern and the second interconnect pattern includes a second lead pattern, such that the route track containing the first lead pattern is immediately adjacent to the route track containing the second lead pattern. Metal interconnect lines are formed in the first interconnect pattern and the second interconnect pattern. A stretch crossconnect is formed in a vertical connecting level, such as a via or contact level, which electrically connects only the first lead and the second lead. The stretch crossconnect is formed concurrently with other vertical interconnect elements.