Two-Transistor Memory Cell With Single Access Line
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Solution Overview
Problem
Conventional volatile memory devices face challenges in reducing memory cell size to increase storage density due to physical limitations and fabrication constraints, leading to inefficiencies in storing and retrieving data.
Innovation Solution
The use of a two-transistor memory cell structure with a floating gate charge storage node, where a single access line controls both transistors, allowing for more compact design and efficient data storage and retrieval without the need for separate charge storage containers like capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional memory cell structures are used, then fabrication processes are well-established, but memory cell size cannot be reduced further due to physical limitations
Solution Approach 1:
The patent merges the charge storage function with the transistor gate structure by using the transistor gate as the charge storage node. This eliminates the need for separate capacitor structures and reduces the memory cell area while maintaining functionality.
Solution Approach 2:
The transistor gate serves multiple functions: it acts as both the control electrode for transistor operation and the charge storage node for data retention. This multi-functionality reduces the number of components needed and shrinks the overall cell size.
2Area of stationary object
If separate charge storage containers like capacitors are used, then data storage is reliable, but memory cell area increases
Solution Approach 1:
The patent extracts the charge storage function from separate capacitor structures and integrates it directly into the transistor gate. This removes the need for additional charge storage containers while maintaining data retention capability.
Solution Approach 2:
The charge storage node is merged with the transistor gate structure, combining the storage function with the switching function in a single component, thereby reducing total cell area while preserving reliability.
3Device complexity
If multiple access lines are used for each transistor, then transistor control is precise, but device complexity increases
Solution Approach 1:
A single access line is designed to control both transistors in the memory cell, making the access line multi-functional. This reduces the number of access lines needed while maintaining the ability to precisely control transistor operation through voltage signaling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of smaller, more efficient volatile memory devices with improved storage density and data retention, overcoming the limitations of conventional techniques by using a single access line to control both transistors and store information as charge in a floating gate structure.
Implementation Method 1
a charge storage node (e.g., structure) that can be a floating gate structure
Implementation Method 2
a single access line controls both transistors, allowing for smaller device size
Data Source
AI summary
Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes multiple two-transistor (2T) memory cells. Each of the multiple 2T memory cells includes: a p-channel field effect transistor (PFET) including a charge storage node and a read channel portion, an n-channel field effect transistor (NFET) including a write channel portion that is directly coupled to the charge storage node of the PFET; a single bit line pair coupled to the read channel portion of the PFET; and a single access line overlapping at least part of each of the read channel portion and the write channel portion.