Two-Transistor Shared Decoding for 3D Memory Pillar Isolation
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Solution Overview
Problem
Existing memory devices with single-transistor architectures face issues with incomplete isolation between pillars and bit lines, leading to transistor degradation, increased leakage current, and decreased device performance over time.
Innovation Solution
Implementing a multi-transistor architecture, such as a two-transistor architecture, where pillars are coupled to bit lines using two transistors, and circuitry is used to bias the gates of these transistors to different voltages, ensuring unselected pillars remain isolated during access operations, reducing electrical stress on transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single-transistor architecture is used to couple pillars to bit lines, then device complexity is reduced, but isolation between unselected pillars and bit lines becomes incomplete leading to increased leakage current and transistor degradation
Solution Approach 1:
The patent divides the single transistor coupling function into two separate transistors: a first transistor for coupling the selected pillar to the bit line, and a second transistor for isolating unselected pillars from the bit line. This segmentation allows independent control of each transistor's state, enabling complete isolation of unselected pillars while maintaining controlled coupling of selected pillars, thereby resolving the contradiction between device complexity and isolation reliability.
2Ease of manufacture
If a single-transistor architecture is used, then manufacturing is simpler, but leakage current increases due to incomplete isolation
Solution Approach 1:
By segmenting the coupling function into two transistors with independent gate control, the patent enables complete isolation of unselected pillars from bit lines. The second transistor specifically targets the isolation function, ensuring that unselected pillars are fully disconnected from bit lines regardless of the first transistor's state. This eliminates the leakage current path that exists in single-transistor architectures, resolving the contradiction between manufacturing simplicity and energy loss.
3Ease of operation
If a single-transistor architecture is used to access memory cells, then device operation is simpler, but transistor degradation accelerates over time
Solution Approach 1:
The patent segments the transistor control function into two independently controlled transistors, where the second transistor is specifically dedicated to isolating unselected pillars. This segmentation ensures that the first transistor only handles selected pillar coupling, reducing its operational stress and degradation from constantly managing both isolation and coupling functions. The simplified access operation is maintained through coordinated control of both transistors, resolving the contradiction between operational simplicity and transistor lifespan.
4Reliability
If a multi-transistor architecture is implemented to improve isolation, then reliability increases, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the isolation and coupling functions into two distinct transistors with specialized roles. The first transistor handles selected pillar coupling while the second transistor handles unselected pillar isolation. This functional segmentation achieves complete isolation reliability while keeping the architecture relatively simple through clear functional division, resolving the contradiction between reliability improvement and device complexity increase.
Data Source
AI summary
Methods, systems, and devices for shared decoder architecture for three-dimensional memory arrays are described. A memory device may include pillars coupled to an access line using two transistors positioned between the pillar and the access line. The gates of the two transistors may be coupled with respective gate lines coupled with circuitry configured to bias the gate line as part of an access operation for a memory cell coupled with the pillar. In some cases, the circuitry may be positioned between tiles of the memory device, at an end of one or more tiles of the memory device, between word line combs of a tile of the memory device, or a combination thereof.