Stacked-Tier 2-Transistor Memory Cells for Higher Storage Density
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Solution Overview
Problem
Conventional volatile memory devices face challenges in increasing storage density due to physical limitations and fabrication constraints when shrinking memory cell size.
Innovation Solution
A memory device with stacked tiers of two-transistor memory cells, utilizing separate conductive regions for access lines and shared data lines, along with a common ground connection, to improve device area efficiency and reduce capacitive coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell size is shrunk to increase storage density, then storage density is improved, but physical limitations and fabrication constraints make it difficult to achieve further shrinkage
Solution Approach 1:
The patent transitions from a planar memory cell layout to a three-dimensional stacked architecture with multiple tiers. Memory cells are arranged in vertical stacks共享 word lines and data lines across multiple levels, effectively utilizing the vertical dimension to increase storage density without further shrinking the footprint of individual cells. This dimensional change allows more cells to be packed into the same device area while avoiding the fabrication constraints of continued lateral scaling.
2Area of stationary object
If memory cell size is reduced, then device area efficiency is improved, but capacitive coupling between adjacent lines increases
Solution Approach 1:
The patent segments the memory cell structure into distinct tiers with separate conductive regions for access lines and shared data lines. By dividing the memory array into multiple tiers that share conductive structures, the design reduces the overall device area while managing capacitive coupling through strategic line sharing and proper spacing between tiers.
Solution Approach 2:
Data lines are designed to be shared across multiple memory cells in different tiers, making them multi-functional. This sharing approach reduces the total number of conductive lines required, thereby reducing device area and minimizing capacitive coupling between adjacent lines while maintaining full functionality across all memory cells.
3Quantity of substance
If more memory cells are packed into a given area, then storage density is improved, but data integrity may be compromised due to increased interference
Solution Approach 1:
By stacking memory cells vertically into multiple tiers, the patent achieves high storage density without increasing lateral interference between cells. The vertical arrangement with shared conductive structures allows more cells to be packed into the same footprint area while maintaining adequate spacing and signal integrity through the three-dimensional architecture.
Data Source
AI summary
Some embodiments include apparatuses and methods of using the apparatuses. One of the apparatuses includes first, second, and third conductive structures, each having a length in a first direction, first and second memory cells spaced apart from each other in a second direction perpendicular to the first direction, first conductive regions, and second conductive regions. Each of the first and second memory cells includes a first semiconductor portion located on a first level of the apparatus and coupled to the third conductive structure and one of the first and second conductive structures, a second semiconductor portion located on a second level of the apparatus and coupled to one of the first and second conductive structures. The first conductive regions are opposite the first and second semiconductor portions, respectively, of the first memory cell. Second conductive regions are opposite the first and second semiconductor portions, respectively, of the second memory cell.