Two-Way Interleaving in Three-Rank Memory Systems
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Solution Overview
Problem
Two-way interleaving techniques are inefficient in three-rank environments, leading to increased system costs and limited memory interleaveability, as they cannot fully utilize the memory resources, resulting in only two-thirds of the memory being effectively interleaved.
Innovation Solution
A memory controller implements a unique mapping of target ranges across three ranks with non-uniform offsets, allowing full two-way interleaving by distributing data across all ranks, ensuring that each range is interleaved at different positions, thereby enabling the entire memory to be utilized effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If two-way interleaving is applied in a three-rank environment using conventional methods, then memory access bandwidth is improved for the interleaved portions, but one-third of the memory (the third rank region) cannot be interleaved, reducing overall system efficiency
Solution Approach 1:
The patent applies different interleaving strategies to different regions of memory. Specifically, it divides the address space into three regions and applies two-way interleaving to two regions while using a different mapping strategy for the third region, allowing all three ranks to participate in interleaving effectively. This local differentiation resolves the contradiction by enabling full memory utilization while maintaining high bandwidth performance.
Solution Approach 2:
The patent introduces asymmetric offset values for the three ranks in the memory mapping. Instead of using uniform offsets for all ranks, it employs different offset values (e.g., offset1, offset2, offset3) for the three regions, enabling the third rank to be fully interleaved alongside the first two ranks. This asymmetric approach allows complete memory interleaveability while preserving performance benefits.
2Productivity
If memory is increased to 64GB to allow full two-way interleaving, then complete memory interleaveability is achieved, but system cost increases considerably due to adding a fourth memory module
Solution Approach 1:
The patent changes the mapping parameters (offsets and base addresses) for the three-rank configuration to enable full interleaving without adding hardware. By adjusting the offset values and base address mappings in the memory controller, it achieves complete memory interleaveability with the existing three-rank configuration, eliminating the need for costly hardware upgrades.
3Ease of manufacture
If conventional two-way interleaving is used in three-rank environments, then implementation simplicity is maintained, but memory utilization efficiency decreases due to one rank remaining non-interleaved
Solution Approach 1:
The patent creates a universal memory mapping scheme that works across all three ranks simultaneously. The mapping mechanism is designed to handle three-rank configurations naturally, making the system multi-functional and adaptable to different memory configurations without requiring complex custom handling for each rank. This maintains implementation simplicity while achieving full memory utilization.
Data Source
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AI summary
A memory controller maintains a mapping of target ranges in system memory space interleaved two-ways across locations in a three-rank environment. For each range of the target ranges, the mapping comprises a two-way interleaving of the range across two ranks of the three-rank environment and offsets from base locations in the two ranks. At least one of the ranges has offsets that differ relative to each other. Such offsets allow the three ranks to be fully interleaved, two ways. An instruction to read data at a rank-agnostic location in the diverse-offset range causes the memory controller to map the rank-agnostic location to two interleaved locations offset different amounts from their respective base locations in their ranks. The controller may then affect the transfer of the data at the two interleaved locations.