Two-Wire Bus Addressing for Simultaneous Module Data Transfer
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Solution Overview
Problem
Two-wire communication protocols suffer from data throughput limitations due to sequential data transmission between a main device and secondary devices, with clock speed enhancements reaching a limit in state-of-the-art systems.
Innovation Solution
Implementing a two-wire bus protocol that configures secondary modules with both unique and common addresses, allowing simultaneous data transmission to multiple modules, and using an interrupt line to manage error detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If sequential communication protocol is used between main device and secondary devices, then device complexity is reduced and ease of operation is improved, but data throughput is limited
Solution Approach 1:
The patent segments the address space into unique addresses and common addresses. Secondary modules are configured with both unique addresses (for individual addressing) and common addresses (for group addressing). This segmentation allows the main module to transmit data to multiple secondary modules simultaneously by using common addresses, thereby increasing data throughput without complicating the basic communication protocol structure
Solution Approach 2:
The communication protocol is enhanced to support multiple functions: it can address individual secondary modules using unique addresses and can simultaneously address multiple secondary modules using common addresses. This multi-functionality allows the same data line and clock line to handle both sequential and simultaneous data transmission modes, improving productivity without requiring additional physical communication channels
2Productivity
If clock speed is increased to improve data throughput, then data transmission speed is improved, but there is a physical limit to how fast two-wire systems can be clocked
Solution Approach 1:
Instead of increasing clock speed along the same dimension (which hits physical limits), the patent introduces a new dimension of parallelism by enabling simultaneous data transmission to multiple secondary modules. By using common addresses, the main module can broadcast data to multiple recipients at once, effectively multiplying the data throughput without increasing the clock frequency
3Productivity
If multiple secondary modules are programmed individually using unique addresses, then manufacturing precision and reliability are maintained, but time required for programming and reconfiguration increases
Solution Approach 1:
Secondary modules are pre-configured with both unique addresses and common addresses during manufacturing or initialization. This preliminary configuration enables rapid reconfiguration later, as the main module can simply activate common addresses to program multiple modules simultaneously, without needing to individually configure each module's address capabilities
Data Source
AI summary
A device, comprising: a main module; a plurality of secondary modules; and a data bus configured to enable data transmission between the main module and the plurality of secondary modules over a data line of the data bus; wherein each of the plurality of secondary modules is configured with a unique secondary address used by the main module to communicate with the respective secondary module over the data line, wherein the main module is operable to configure a first two or more of the plurality of secondary modules with a first common secondary address for simultaneous data transmission from the main module to the first two or more of the plurality of secondary modules over the data line.