Two-Wire Bus Clock Sustain for Slave Node Power Management
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Solution Overview
Problem
The proliferation of electronic components in devices like automobiles and robotic systems leads to excessive wiring, increasing system complexity, weight, and decreasing performance and reliability due to the conventional communication infrastructure used for signal exchange.
Innovation Solution
A two-wire bus communication system that provides low latency, time division multiplexed (TDM) communications, enabling bi-directional synchronous data, clock, and synchronization signals, allowing for direct point-to-point connections between nodes and supporting multiple daisy-chained nodes, with power transmission over the same bus, eliminating the need for thick cables.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional communication infrastructure is used to exchange signals between components, then reliable communication can be achieved, but the system requires thick and heavy bundles of cables, increasing device complexity and weight
Solution Approach 1:
The patent combines multiple communication functions (data transmission, clock signaling, synchronization, and power delivery) into a single two-wire bus interface. This merging of functions eliminates the need for separate cables for each signal type, thereby reducing wiring complexity while maintaining communication reliability through integrated protocol management
Solution Approach 2:
The two-wire bus is designed to perform multiple functions simultaneously: it carries bidirectional data, transmits clock signals, provides synchronization information, and delivers power to remote devices. This multi-functionality allows a single cable pair to replace traditional multi-cable infrastructure, reducing system complexity without compromising communication reliability
2Adaptability or versatility
If more components are included in devices to increase performance, then functionality is improved, but the communication infrastructure requires more cables, increasing weight and complexity
Solution Approach 1:
The two-wire bus provides a universal communication interface that can connect multiple diverse components (sensors, actuators, control units) using the same protocol and physical medium. This allows the system to accommodate increased functionality and component count without proportionally increasing cable weight, as all components share the same lightweight two-wire infrastructure
Solution Approach 2:
The system segments the communication network into multiple independent nodes that can be daisy-chained along the two-wire bus. Each node operates independently but communicates through the shared bus, allowing the system to scale in functionality by adding nodes rather than requiring dedicated cables for each component, thereby limiting cable weight growth
3Reliability
If traditional communication infrastructure is used, then signal exchange between components is possible, but performance decreases due to excessive wiring
Solution Approach 1:
By merging data, clock, and synchronization signals onto a single two-wire bus with integrated protocol handling, the system reduces the overhead and latency associated with managing multiple separate cable connections. This streamlined approach improves system performance while maintaining communication capability through the unified interface
Data Source
AI summary
Disclosed herein are systems and methods for clock sustain in a two-wire communication systems and applications thereof. In some embodiments, in a clock sustain state, slave nodes with processors and digital to analog converters (DACs) may be powered down efficiently in the event of lost bus communication. For example, when the bus loses communication and a reliable clock cannot be recovered by the slave node, the slave node may enter the sustain state and, if enabled, signals this event to a general purpose input/output (GPIO) pin. In the clock sustain state, the slave node phase lock loop (PLL) may continue to run for a predetermined number of SYNC periods, while attenuating the inter-integrated circuit transmit (I2S DTXn) data from its current value to 0. After the predetermined number of SYNC periods, the slave node may reset and reenter a power-up state.