Two-Wire Communication Timing Using Clock Pulse Counting
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Solution Overview
Problem
Existing two-wire communication systems face limitations in increasing transmission rate without raising pulse signal frequency, due to rounded rising and falling edges of the pulse signal, and varying delay times that require additional time for data communication.
Innovation Solution
A communication apparatus with a clock generating unit producing a higher frequency clock signal, a counting unit to count pulses, and a transmitting unit that adjusts electric current based on data values and determines data switch timing within a cycle, allowing for increased data transmission efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the frequency of the pulse signal is increased to increase communication speed, then the transmission rate is improved, but the rising edge and falling edge become more rounded due to driving circuit characteristics, limiting further frequency increases
Solution Approach 1:
The patent introduces a sampling clock as an intermediary signal with higher frequency than the pulse signal. This sampling clock mediates the data sampling process, allowing data to be sampled at optimal points within the pulse cycle without requiring the pulse signal itself to have high frequency or sharp edges. The sampling clock acts as a bridge between the slow pulse signal and the fast data processing requirements.
Solution Approach 2:
The system performs preliminary actions by pre-determining the sampling timing based on the pulse signal characteristics before actual data transmission. The sampling clock is generated and synchronized in advance, and the sampling points are predetermined within each pulse cycle, allowing the system to prepare for data capture without waiting for the pulse edges to be sharp.
2Reliability
If the control apparatus waits for a sufficient margin time to account for delay time variation when reading data, then data reception reliability is improved, but the time required for data communication increases
Solution Approach 1:
The system uses feedback by monitoring the actual delay time td through the sampling process. By sampling data at multiple points within the pulse cycle using the high-frequency sampling clock, the system can determine the actual delay characteristics and adjust subsequent sampling timing accordingly. This feedback mechanism eliminates the need for excessive margin time while maintaining reliable data reception.
Solution Approach 2:
The sampling timing is made dynamic rather than static. Instead of using a fixed margin time for all conditions, the system dynamically adjusts the sampling points within the pulse cycle based on the actual delay time td observed in each communication session. This dynamic adaptation allows the system to minimize waiting time while ensuring reliable data capture under varying conditions.
Data Source
AI summary
A communication apparatus includes a first terminal that receives a reference voltage, a second terminal that receives a pulse signal, and at least one processor to execute instructions. The instructions are executed to generate a clock signal that has a frequency higher than a frequency of the received pulse signal, count a number of pulses of the clock signal and determine a count value counted during a first cycle that is a cycle of the pulse signal to the second terminal, and, during a period of data transmission, increase or decrease an electric current that flows between the communication apparatus and the external apparatus according to a data value of data to be transmitted to the external apparatus. Data is transmitted to the external apparatus at least once during the first cycle, and data switch timing during the first cycle is based on the count value.