Two-Wire TDM Bus for Low-Latency Node Communication
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Solution Overview
Problem
The proliferation of electronic components in devices like automobiles leads to excessive wiring, increasing system complexity, weight, and decreasing performance and reliability due to the existing communication infrastructure.
Innovation Solution
A low-latency, time division multiplexed (TDM) two-wire communication system that uses a twisted wire pair for bi-directional synchronous data, clock, and synchronization signals, enabling direct point-to-point connections between nodes and supporting power transmission over the same bus, allowing multiple nodes to contribute or consume channel content.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional communication infrastructure is used to connect electronic components, then reliable communication can be achieved, but wiring complexity and weight increase excessively
Solution Approach 1:
The patent combines multiple communication functions (data transmission, clock signaling, synchronization) and power delivery into a single two-wire bus system. This merging of previously separate communication channels into one unified interface reduces wiring complexity while maintaining communication reliability through protocol-level error handling and synchronization mechanisms.
Solution Approach 2:
The two-wire bus is designed to perform multiple functions simultaneously: bidirectional data communication, clock distribution, synchronization signaling, and power transmission. This multi-functionality eliminates the need for separate dedicated lines for each function, thereby reducing overall wiring complexity while preserving reliable communication across all functions.
2Adaptability or versatility
If more electronic components are included in devices, then functionality increases, but wiring complexity and weight increase
Solution Approach 1:
By merging multiple communication and power functions into a single two-wire bus, the system can support additional electronic components without proportionally increasing wiring weight. The unified bus architecture allows new components to be integrated into the existing two-wire network rather than requiring additional dedicated cables.
Solution Approach 2:
The patent transitions from a spatial dimension approach (adding more physical wires for each component) to a temporal dimension approach (using time-division multiplexing to share the two-wire bus among multiple components). This allows multiple components to communicate over the same physical medium at different time slots, supporting increased functionality without increased wiring weight.
3Reliability
If traditional communication infrastructure is used, then component connectivity is achieved, but performance decreases due to excessive wiring
Solution Approach 1:
The consolidation of multiple functions into a single two-wire bus reduces signal interference and impedance mismatches that occur with multiple separate cables. This merging improves signal integrity and reduces communication errors, thereby enhancing both reliability and performance simultaneously through cleaner signal paths and simplified impedance matching.
Data Source
AI summary
Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.