Two-Bit MRAM Cell Architecture Shared Transistor Design
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current single-bit MRAM device architectures require one transistor for each cell, limiting bit density due to the one-to-one ratio and the need for large transistors to support driving current, which impedes scaling and efficiency.
Innovation Solution
A two-bit MRAM cell architecture that uses one shared transistor for two single-bit MRAM cells, incorporating selector devices to prevent unintended access and interference, allowing independent read and write operations through the use of selector switches or diodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If one transistor is used for each single-bit MRAM cell, then reliable read and write operations can be performed, but the bit density is limited due to the one-to-one ratio and the need for large transistors to support driving current
Solution Approach 1:
The patent combines two single-bit MRAM cells into a two-bit MRAM cell that shares a common transistor. The two cells are connected in parallel to the shared transistor, allowing both cells to use the same transistor for read and write operations. This merging approach reduces the transistor-to-cell ratio from 1:1 to 1:2, thereby doubling the bit density while maintaining reliable operations through the shared transistor infrastructure.
Solution Approach 2:
The shared transistor in the two-bit MRAM cell architecture serves multiple functions: it can selectively access either of the two single-bit cells for read operations, write operations, or both simultaneously. The transistor's gate is controlled by word lines that can independently select which cell to access, enabling the single transistor to universally serve multiple storage locations without compromising operational reliability.
2Ease of operation
If one transistor is used for each single-bit MRAM cell, then independent cell access is simplified, but the number of transistors increases, reducing memory capacity and efficiency
Solution Approach 1:
The patent merges the transistor infrastructure of two single-bit cells into a shared resource. Instead of having two separate transistors, the architecture uses one common transistor that both cells share for access operations. This reduction in transistor count from two to one per two-bit cell decreases device complexity while the word line control mechanism maintains the ability to independently access each cell.
Solution Approach 2:
The patent introduces word lines as intermediary control elements that mediate between the control logic and the shared transistor. The word lines can independently activate or deactivate the shared transistor for accessing either cell, providing an intermediary layer that simplifies independent cell access despite the shared transistor architecture. This mediator approach allows complex sharing arrangements to be controlled through simple line activations.
3Productivity
If small transistors are used to increase bit density, then more cells can be packed, but the driving current is insufficient for reliable operations
Solution Approach 1:
The patent combines the current requirements of two single-bit cells into a single shared transistor. The shared transistor only needs to provide sufficient current for one cell at a time (since cells are accessed independently), rather than each transistor needing to drive its own cell. This allows the use of larger transistors with adequate drive current while maintaining high bit density through the shared architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This architecture reduces the number of transistors required by half, enabling higher bit density and larger transistors with increased drive current, thus improving memory capacity and efficiency.
Implementation Method 1
MRAM stores the data in magnetic domains using magnetic storage elements. The magnetic storage elements are formed from two ferromagnetic plates, each of which can hold a magnetization
Implementation Method 2
The magnetic storage elements are formed from two ferromagnetic plates, each of which can hold a magnetization
Implementation Method 3
One of the two plates is a permanent magnet set to a particular polarity
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A magnetoresistive random-access memory (MRAM) device includes a first cell selectively connected to a first bit line and a second cell selectively connected to a second bit line. The MRAM device further includes a shared transistor connected to the first cell and connected to the second cell. The MRAM device further includes a first selector device and a second selector device. The first selector device is configured to permit current to flow through the first cell to the shared transistor when a voltage applied to the first selector device is larger than a threshold activation voltage. The second selector device is configured to permit current to flow through the second cell to the shared transistor when a voltage applied to the second selector device is larger than a threshold activation voltage. The MRAM cell further includes a word line connected to a gate of the shared transistor.