Two-Cycle Delay ATPG Patterns for Multicycle Fault Detection
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Solution Overview
Problem
Current testing methods for integrated circuit (IC) chips are inadequate in detecting multicycle faults and defects within IC cells, as they primarily focus on faults between cell instances or at cell I/O ports, neglecting internal circuit faults.
Innovation Solution
The development of two-cycle delay test patterns using ATPG techniques that target multicycle faults and defects, employing a scan-in shift window at a test clock frequency and a capture window with a launch and capture cycle at a functional clock frequency greater than the test clock frequency, along with sim-shifting to simulate faults and provide additional initialization cycles for detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard ATPG test patterns are used to test IC chips, then faults between cell instances and at cell I/O ports can be detected, but multicycle faults and defects within IC cells cannot be detected
Solution Approach 1:
The patent applies preliminary action by performing sim-shifting during the scan-in shift window to pre-initialize the circuit state before actual test pattern application. This pre-initialization ensures that multicycle faults are properly set up for detection without requiring separate explicit multicycle test patterns, thereby resolving the contradiction between detecting multicycle faults and maintaining test pattern versatility.
Solution Approach 2:
The patent changes the timing parameters by operating the scan-in shift window at a test clock frequency and the capture window at a functional clock frequency greater than the test clock frequency. This parameter change enables the detection of multicycle faults by creating the necessary time conditions for fault propagation while maintaining compatibility with standard test patterns.
2Reliability
If explicit multicycle test patterns are generated to detect multicycle faults, then detection capability improves, but the number of test patterns increases
Solution Approach 1:
The patent makes standard ATPG test patterns multi-functional by enabling them to detect both single-cycle and multicycle faults through sim-shifting. This universality allows existing test patterns to serve dual purposes, improving multicycle fault detection without increasing the number of test patterns, thereby resolving the contradiction between detection capability and test time.
Solution Approach 2:
The patent applies self-service by using the scan-in shift window itself to perform the initialization function traditionally requiring separate multicycle test patterns. The scan-in process automatically initializes the circuit state for multicycle fault detection without needing additional dedicated initialization patterns, reducing test time while maintaining detection capability.
3Reliability
If test patterns are applied at functional clock frequency, then multicycle faults can be detected, but test application complexity increases
Solution Approach 1:
The patent segments the test process into two distinct phases: a scan-in shift window operating at test clock frequency for pattern application and initialization, and a capture window operating at functional clock frequency for fault detection. This segmentation allows each phase to operate at its optimal frequency without increasing overall test complexity, as the automation handles the frequency transitions.
Data Source
AI summary
An IC test engine generates a plurality of two-cycle delay test patterns that target a first set of multicycle faults and/or defects of a fabricated IC chip based on an IC design. Each two-cycle delay test pattern includes a scan-in shift window operating at a test clock frequency, and a capture window with a launch cycle and a capture cycle operating at a functional clock frequency. The IC test engine fault simulates the plurality of two-cycle delay test patterns against a second set of multicycle faults and/or defects in the IC design utilizing sim-shifting, such that a state of the IC design after at least a last two shift clock cycles of a scan-in shift in window of each two-cycle delay test pattern of the plurality of two-cycle delay test patterns are fault simulated to provide two fault initialization cycles for detection of a multicycle delay fault and/or defect.