Two-Pin Scan-Testing for Low Pin Count Digital Circuits
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Solution Overview
Problem
Digital integrated circuits with a low pin count face challenges in scan-testing, as conventional methods require five distinct pins, which is not feasible for circuits with only four pins, including two power supply pins, a clock pin, and a single use pin.
Innovation Solution
The circuit configures the use pin to receive and output serial data at a clock signal rate, switching between input and output modes to perform scan-testing, utilizing a test initialization sequence to determine vector size and capture phase parameters, and employing a state machine to manage the pin's transfer direction, allowing for full scan-testing with only two signal pins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional scan-test methods are used requiring five distinct pins, then complete test functionality is achieved, but pin count requirement increases to 8 pins including power supply pins
Solution Approach 1:
The patent combines multiple test signal functions into a single use pin. The use pin serves as both scan-in (SC-IN) and scan-out (SC-OUT) by dynamically switching its direction based on test phase, eliminating the need for separate dedicated pins for each function.
Solution Approach 2:
The use pin is designed to perform multiple functions: it can receive test vectors during scan-in phase, output test results during scan-out phase, and switch between input and output modes. This multi-functional design reduces the total pin count while maintaining complete test capability.
2Quantity of substance
If the use pin is used for both input and output operations, then pin count is reduced to four pins, but the complexity of managing pin transfer direction increases
Solution Approach 1:
The circuit autonomously manages the use pin's direction switching through an internal state machine that automatically transitions the pin between input and output modes based on the test phase, without requiring external control signals.
Solution Approach 2:
The use pin's electrical characteristics are dynamically changed during operation. The pin switches between input and output modes under control of internal logic that responds to test phase transitions, making the pin configuration adaptive rather than static.
Data Source
AI summary
A method for scan-testing of an integrated circuit includes the following steps carried out by the circuit itself: upon powering on of the circuit, watching for bit sequences applied to a use pin configured for receiving serial data from the exterior at the rate of a clock signal applied to a clock pin; configuring the circuit in a test mode when a bit sequence is identified as a test initialization sequence; connecting latches of the circuit in a shift register configuration, and connecting the shift register for receiving a test vector in series from the use pin; switching the transfer direction of the use pin to the output mode for providing to the exterior serial data at the rate of the clock signal; and connecting the shift register for providing its content, as a test result set, in series on the use pin.