Two-Port SRAM Cell With Segmented Vss Lines
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Solution Overview
Problem
SRAM cells face challenges in balancing speed and power consumption, with higher threshold voltage needed for cell stability and standby leakage reduction in the data storage and write port, while lower threshold voltage in the read port results in high leakage due to subthreshold leakage, necessitating innovative design techniques to manage these competing requirements.
Innovation Solution
The SRAM cell structure incorporates a two-port design with distinct Vss lines for the read and write ports, utilizing FinFET transistors with varying numbers of fins and power saving circuits to selectively apply different Vss potentials, reducing leakage during non-read cycles and enhancing read-port performance during read cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If higher threshold voltage is used in the data storage and write port, then cell stability and standby leakage reduction are improved, but read port performance deteriorates due to high leakage from subthreshold leakage
Solution Approach 1:
The patent divides the SRAM cell into separate write port and read port sections, each with independent Vss lines. The write port uses a first Vss line with higher threshold voltage for stability, while the read port uses a second Vss line with lower threshold voltage for reduced subthreshold leakage during read operations. This segmentation allows each port to have optimized threshold voltages without compromising the other.
Solution Approach 2:
The patent applies different threshold voltage characteristics to different parts of the SRAM cell. The write port devices are designed with higher threshold voltage for stability, while the read port devices are designed with lower threshold voltage to reduce subthreshold leakage during read cycles. This local optimization resolves the contradiction by tailoring device parameters to specific functional requirements.
2Object-generated harmful factors
If lower threshold voltage is used in the read port, then subthreshold leakage is reduced, but cell stability deteriorates
Solution Approach 1:
The patent separates the power supply lines into first Vss line for the write port and second Vss line for the read port. This allows the read port to operate with lower threshold voltage for reduced subthreshold leakage while the write port maintains higher threshold voltage for stability. The segmentation isolates the stability requirement from the leakage reduction requirement.
Solution Approach 2:
The read port devices are specifically designed with lower threshold voltage characteristics to minimize subthreshold leakage during read operations, while the write port devices maintain higher threshold voltage for stability. This local parameter optimization allows each section to be tuned for its specific functional needs without compromising overall cell reliability.
3Object-generated harmful factors
If distinct Vss lines are used for read and write ports, then leakage is reduced during non-read cycles, but device complexity increases
Solution Approach 1:
The patent introduces separate first Vss line and second Vss line for the write port and read port respectively. This segmentation enables independent voltage control for each port, allowing the read port to have lower threshold voltage during read cycles while the write port maintains higher threshold voltage during standby, thereby reducing overall leakage.
Solution Approach 2:
The patent implements dynamic voltage selection where the threshold voltage for the read port can be changed based on operational state. During read cycles, the second Vss line provides lower threshold voltage to reduce subthreshold leakage, while during non-read cycles, the system can switch to higher threshold voltage to minimize standby leakage. This dynamic adjustment optimizes power consumption.
Data Source
AI summary
A memory cell is provided. The memory cell comprises a write port and a read port. The write port comprises a pair of cross-coupled inverters and a plurality of metal lines. The first inverter comprises a first pull-up device and a first pull-down device. The second inverter comprises a second pull-up device and a second pull-down device. The metal lines comprise a Vcc conductor line, a first Vss conductor line, and a second Vss conductor line. The first pull-down device has a source terminal coupled to the first Vss line. The second pull-down device has a source terminal coupled to the second Vss line. The read port comprises a cascaded device, a read word line, read bit line and a third Vss conductor line. The cascaded device comprises a read pull-down device and a read pass device. The read pull-down device has a source terminal coupled to the third Vss conductor line. The read pass device has a drain terminal coupled to the read bit line. The third Vss conductor line is coupled to a first power saving circuit. The Vcc conductor line is coupled to a second power saving circuit.