Two-Port SRAM Shared Decoder Double-Pumped Access
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing two-port SRAM circuits require double the die area of one-port SRAM circuits, making them an expensive design option, and increasing the access clock speed to achieve adequate bandwidth is not feasible in high-performance designs due to power and operational constraints.
Innovation Solution
A two-port SRAM design with a shared decoder architecture and six-transistor (6T) SRAM cells that operate with mutually synchronous read and write ports, eliminating one pre-charge cycle and allocating one read and one write time slot per clock cycle, allowing for edge-triggered clocking and area-efficient implementation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a two-port SRAM circuit is used to provide independent read and write access, then system performance and bandwidth are improved, but die area increases to approximately double that of a one-port SRAM
Solution Approach 1:
The patent merges the read and write port functions into a single port structure that can perform both operations sequentially. The shared decoder architecture combines the address decoding functions for both ports, and the multiplexed word line control integrates the read and write timing control into a single mechanism, thereby reducing the overall circuit area while maintaining two-port functionality.
Solution Approach 2:
The single port structure is designed to be universal, capable of performing both read and write operations depending on the control signals. The port can be configured as a read port or write port based on the enable signals, allowing one physical port to serve multiple functions that traditionally required separate ports.
2Productivity
If the access clock speed is doubled to provide adequate bandwidth, then read and write bandwidth requirements are met, but power consumption increases substantially and reliability decreases
Solution Approach 1:
The patent implements periodic action by using a dual-pumped clocking scheme where the word line is activated twice per clock cycle - once for read operations and once for write operations. This periodic activation pattern allows the single port to service both read and write requests sequentially within one clock period, maintaining bandwidth without requiring doubled clock frequency.
Solution Approach 2:
The design ensures continuity of useful action by seamlessly alternating between read and write operations within the same clock cycle. The multiplexed word line control ensures that the memory array is continuously accessible through the single port, eliminating idle time and maintaining steady throughput without requiring higher clock frequencies.
3Productivity
If the access clock speed is doubled to achieve adequate bandwidth, then read and write bandwidth requirements are met, but the SRAM may not be able to operate reliably at twice the already aggressive clock frequency
Solution Approach 1:
The patent applies dynamics by implementing a flexible timing control mechanism that can adapt the word line activation timing based on the operational mode. The dual-pumped clocking system allows dynamic adjustment of the read and write timing within each clock cycle, enabling the system to maintain reliable operation at the original clock frequency while achieving two-port bandwidth performance.
4Area of stationary object
If a one-port SRAM circuit operating at twice the access clock speed is used, then die area is reduced, but substantial additional power is required and the design becomes less adaptable to different usage models
Solution Approach 1:
The patent implements dynamics through its configurable port operation mode. The single port can be dynamically configured to function as a read-only port, write-only port, or bidirectional port based on the control signals provided. This dynamic configurability allows the same physical circuit to adapt to different usage models and applications without requiring hardware changes.
Data Source
AI summary
One embodiment of the present invention sets forth a synchronous two-port static random access memory (SRAM) design with the area efficiency of a one-port SRAM. By restricting both access ports to an edge-triggered, synchronous clocking regime, the internal timing of the SRAM can be optimized to allow high-performance double-pumped access to the SRAM storage cells. By double-pumping the SRAM storage cells, one read access and one write access are possible per clock cycle, allowing the SRAM to present two external ports, each capable of performing one transaction per clock cycle.