Two-Transistor DRAM Cell with Common Capacitor
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Solution Overview
Problem
Current DRAM embedded logic processes face challenges in achieving large enough DRAM capacitors with reasonable area without special process steps, leading to voltage drops and increased power consumption due to smaller capacitance and frequent refresh requirements, which conflict with the requirements of compact chip size, high bandwidth, and low power consumption in mobile devices.
Innovation Solution
The semiconductor memory device incorporates a DRAM cell structure with two synchronously operated complementary word-lines, an N-type transistor, a P-type transistor, and a common capacitor, where the common capacitor is arranged between the transistors and consists of three parallelly-connected capacitor elements to enhance capacitance without increasing layout area, thereby reducing on-resistance and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional one-transistor DRAM cells are used, then the chip area is reduced, but the capacitance becomes too small leading to voltage drops and frequent refresh requirements
Solution Approach 1:
The patent merges two transistor structures with a common capacitor to form a two-transistor DRAM cell. This combination allows the capacitor to be shared between two transistors, effectively doubling the storage capacity per capacitor while maintaining compact area. The common capacitor serves both transistors, providing sufficient capacitance to prevent voltage drops and reduce refresh frequency, thus resolving the contradiction between small area and adequate capacitance stability.
Solution Approach 2:
The common capacitor in the two-transistor DRAM cell structure performs multiple functions: it stores data for both transistors, reduces the total number of capacitors needed, and provides sufficient capacitance value to maintain voltage stability. This multi-functional design allows the capacitor to serve the entire memory array efficiently, improving reliability without proportionally increasing area.
2Reliability
If capacitor size is increased to improve capacitance, then the layout area increases, but compact chip size is required
Solution Approach 1:
By merging two transistor-capacitor units into a two-transistor cell with a common capacitor, the patent achieves higher effective capacitance per unit area. The shared capacitor structure allows the layout to be more compact than two separate one-transistor cells would require, as the capacitor serves dual purposes and can be positioned to optimize space utilization.
Solution Approach 2:
The patent utilizes three-dimensional capacitor structures (such as stacked or cylindrical capacitors) to increase capacitance without proportionally increasing the planar layout area. By extending the capacitor design into the vertical dimension or using compact geometries, the invention achieves higher capacitance values while maintaining compact two-dimensional footprint suitable for dense memory arrays.
3Area of stationary object
If smaller capacitance is used, then the chip area is reduced, but power consumption increases due to frequent refresh requirements
Solution Approach 1:
The two-transistor cell with common capacitor achieves sufficient capacitance value to extend refresh intervals, thereby reducing the frequency of refresh operations. This merged structure provides adequate charge storage capacity that maintains voltage levels for longer periods, directly reducing the number of refresh cycles needed and lowering standby power consumption while keeping the area compact.
4Reliability
If boosted voltage is used to improve memory access speed, then the sensing margin is improved, but power consumption and device complexity increase
Solution Approach 1:
The two-transistor cell structure with common capacitor provides inherent noise immunity and improved sensing margin through differential sensing capabilities. By using two transistors that can be differentially switched, the circuit naturally provides better signal discrimination without requiring additional boosted voltage generation circuits, thus improving sensing margin while reducing device complexity.
Data Source
AI summary
A semiconductor memory device is provided such as a random-access memory (DRAM) including a plurality of DRAM memory cells. Each of the DRAM cells includes an N-type transistor, a P-type transistor, and a common capacitor. The components are disposed in the same direction as the bit-line, with the common capacitor occupying the center region between the N- and P-type transistors. The common capacitor is a metal insulator metal (MIM) capacitor configured by connecting three capacitor elements in parallel. The three capacitors include a first capacitor element formed on a first source/drain region of the N-type transistor, a second capacitor element formed on a first source/drain region of the P-type transistor, and a third element over the field isolation region between the transistors. A bottom electrode of each of these capacitor elements connects the first source/drain region of the N-type transistor to a first source/drain region of the P-type transistor.