TWV Dishing Correction via Planarization Layer

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Solution Overview

Problem

Through wafer vias (TWVs) in IC chip fabrication present challenges due to their large dimensions, leading to topography issues during chemical mechanical polish (CMP), causing material puddling and shorts in damascene copper processes, and complicating simultaneous filling of TWVs and standard contacts with titanium nitride and tungsten metallization.

Innovation Solution

The method involves forming TWVs into a substrate with a first dielectric layer, followed by a second dielectric layer that covers the TWV, allowing for separate processes to create contacts and a metal wiring layer that contacts the TWV, thereby preventing copper puddling and shorts by providing a smoother surface for deposition.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If through wafer vias are formed with large dimensions for current IC chip technology, then the via filling capability is improved, but severe topography (dishing or erosion) occurs during CMP process

Engineering Contradiction:

Improvevia filling capabilityVSAvoidsurface topography

Core Design Contradiction:

Manufacturing precisionVSShape

Solution Approach 1:

The patent applies preliminary action by forming a planarization layer of dielectric material over the TWV structure before subsequent metal deposition. This planarization layer pre-compensates for the topography issues, creating a flat surface that prevents copper puddling during later CMP and deposition processes

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary planarization layer between the TWV structure and the metal wiring layers. This intermediary layer acts as a mediator that smooths out the severe topography caused by large TWV dimensions, allowing subsequent metal deposition to occur on a flat surface without causing shorts or puddling

Inventive Principle:

Principle #24Intermediary (Mediator)

2Manufacturing precision

If damascene copper process is used with large TWV dimensions, then via filling is improved, but copper puddling and shorts occur due to topography

Engineering Contradiction:

Improvevia filling capabilityVSAvoidshort prevention

Core Design Contradiction:

Manufacturing precisionVSReliability

Solution Approach 1:

The planarization layer is formed in advance before copper deposition to pre-establish a flat surface. This preliminary action ensures that when copper is deposited in the damascene process, it does not form puddles that would cause shorts, thereby maintaining reliability while still achieving proper via filling

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The planarization layer serves as an intermediary between the rough TWV structure and the copper metal layer. It mediates the interaction by providing a flat interface that prevents direct contact between excess copper and adjacent structures, eliminating the short circuit risk while allowing complete via filling

Inventive Principle:

Principle #24Intermediary (Mediator)

3Manufacturing precision

If titanium nitride and tungsten metallization processes are used for TWVs, then via filling is achieved, but simultaneous filling of TWV and standard contacts becomes complex

Engineering Contradiction:

Improvevia filling capabilityVSAvoidmetallization process complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent segments the metallization process by separating TWV filling from standard contact filling. The planarization layer creates distinct processing zones, allowing different metallization sequences for TWVs and standard contacts, thereby reducing process complexity while maintaining filling effectiveness for both structures

Inventive Principle:

Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach prevents copper puddling and shorts by ensuring a smooth surface for metal deposition, allowing for effective filling of TWVs and standard contacts without topography-induced issues, enhancing the reliability of IC chip fabrication.

Implementation Method 1

The large width results in a very high local pattern factor during chemical mechanical polish (CMP) of the TWVs at the contact level. Consequently, severe topography (approximately 100 nanometers (nm) or greater) may result due to dishing or erosion during CMP.

Methodology Applied

Scientific EffectChemical mechanical polishing:

Data Source

PatentUS7859114B2IC chip and design structure with through wafer vias dishing correction

Publication Date: 2010.12.28 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

An IC chip and design structure having a TWV contact contacting the TWV and extending through a second dielectric layer over the TWV. An IC chip may include a substrate; a through wafer via (TWV) extending through at least one first dielectric layer and into the substrate; a TWV contact contacting the TWV and extending through a second dielectric layer over the TWV; and a first metal wiring layer over the second dielectric layer, the first metal wiring layer contacting the TWV contact.