Through Wafer Vias Dishing Correction via Segmented CMP
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Through wafer vias (TWVs) in IC chip fabrication present challenges due to their large dimensions, leading to topography issues during chemical mechanical polish (CMP), causing material puddling and shorts in damascene copper processes, and complicating simultaneous filling of TWVs and standard contacts with titanium nitride and tungsten metallization.
Innovation Solution
The method involves forming TWVs into a substrate with multiple dielectric layers, planarizing to create smooth surfaces, and forming contacts and metal wiring layers separately to prevent material puddling and ensure proper contact formation, allowing for the use of copper wiring without causing shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If through wafer vias are formed with large dimensions for IC chip fabrication, then the via filling capability is improved, but severe topography and dishing occur during CMP process
Solution Approach 1:
The patent segments the CMP process into multiple steps with different polishing conditions. First, a coarse CMP removes excess material, then a fine CMP with adjusted parameters corrects the dishing. This segmentation allows each step to optimize for its specific function, resolving the contradiction between removing material and maintaining surface flatness.
Solution Approach 2:
The patent changes CMP process parameters between steps - specifically adjusting polishing pressure, slurry flow rate, and pad conditions. The first CMP uses higher pressure for material removal, while the second CMP uses reduced pressure and modified slurry to correct dishing, thus resolving the topography issue while maintaining via filling capability.
2Loss of substance
If chemical mechanical polish is performed on through wafer vias with large dimensions, then material removal is improved, but severe dishing and erosion occur
Solution Approach 1:
The patent divides the CMP operation into two distinct segments: a first CMP step optimized for material removal with higher polishing pressure, and a second CMP step optimized for surface flatness with reduced pressure. This segmentation allows aggressive material removal without permanent dishing, as the second step corrects the topography.
Solution Approach 2:
The first CMP step performs preliminary material removal to clear excess dielectric material from the via regions. This preliminary action creates the necessary via opening, while the subsequent second CMP step performs the corrective action to eliminate dishing, thus resolving the contradiction between removal and shape preservation.
3Manufacturing precision
If damascene copper process is used with severe topography, then via filling is improved, but material puddling and shorts occur
Solution Approach 1:
The patent performs preliminary CMP steps to create a flat surface before copper deposition. This preliminary surface preparation ensures uniform copper film deposition across the wafer, preventing puddling in low-lying areas and ensuring reliable via filling without shorts.
Solution Approach 2:
The patent changes the surface topology parameter by performing CMP to reduce topography variations. This parameter change creates a uniform baseline surface that allows subsequent copper deposition to proceed without puddling, thus resolving the contradiction between via filling and short prevention.
4Manufacturing precision
If titanium nitride and tungsten metallization are used for through wafer vias, then via formation is improved, but simultaneous filling of TWV and standard contacts becomes complex
Solution Approach 1:
The patent segments the metallization filling process into separate operations for through wafer vias and standard contacts. TWVs are formed and filled first using TiN/W metallization, then standard contacts are formed subsequently. This temporal and procedural segmentation simplifies the overall process by avoiding the need for simultaneous multi-material deposition.
Solution Approach 2:
Instead of attempting to fill both TWVs and standard contacts simultaneously with different materials (the conventional complex approach), the patent inverts the sequence by filling TWVs first with TiN/W, then forming standard contacts afterward. This reversal of the conventional sequence dramatically reduces process complexity while maintaining via formation quality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents copper puddling and shorts by creating a smooth surface for metal deposition, enabling effective contact formation and reducing topography-related issues, thus improving the reliability of TWVs and standard contacts in IC chip fabrication.
Implementation Method 1
severe topography (approximately 100 nanometers (nm) or greater) may result due to dishing or erosion during CMP
Data Source
AI summary
Methods of forming through wafer vias (TWVs) and standard contacts in two separate processes to prevent copper first metal layer puddling and shorts are presented. In one embodiment, a method may include forming a TWV into a substrate and a first dielectric layer over the substrate; forming a second dielectric layer over the substrate and the TWV; forming, through the second dielectric layer, at least one contact to the TWV and at least one contact to other structures over the substrate; and forming a first metal wiring layer over the second dielectric layer, the first metal wiring layer contacting at least one of the contacts.