TX Driver Architecture With Fewer Serializers for 112 Gb/s USR
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Solution Overview
Problem
Conventional TX drivers for high-speed serial link applications, such as 112 Gb/s USR, face challenges in meeting stringent area and power consumption requirements due to high power consumption and large capacitive load, making them unsuitable for ultra-short reach applications.
Innovation Solution
A TX driver architecture that includes signal generation, storage, selection, and DAC circuitry to select and convert programmable transmit levels into analog signals, reducing the number of serializers and buffers, thereby minimizing area, power, and capacitance at driver outputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a conventional DAC based TX driver is used, then the output stage has minimal capacitive load at driver outputs, but the driver requires one serializer for every bit of the DAC (e.g., 5 serializers for 5-bit DAC), significantly increasing power and area
Solution Approach 1:
The patent combines multiple serializer functions into a single serializer by using a tap-delay block to generate multiple delayed versions of the input signal. This single serializer then outputs fewer full-rate signals (e.g., 2 signals) that are combined with delayed versions through addition circuits to produce the required number of DAC input signals, eliminating the need for multiple independent serializers.
Solution Approach 2:
The patent segments the signal generation process into multiple stages: a single serializer generates base signals, tap-delay blocks create delayed versions, and addition circuits combine these segments to form the complete set of DAC input signals. This segmentation allows one serializer to perform the work of multiple serializers.
2Device complexity
If a conventional tap-delay block based TX driver is used, then the number of serializers and DPL/AFE interface area is reduced, but a tap-delay data generator block is required that consumes higher power
Solution Approach 1:
The patent extracts the power-consuming tap-delay data generator block from the system by using a different approach: instead of generating tap-delay data digitally and converting it, the system uses analog tap-delay blocks that directly delay the serialized signals. This eliminates the need for the high-power digital data generator while maintaining the tap-delay functionality.
3Device complexity
If a conventional tap-delay block based TX driver is used, then fewer serializers are required, but many slices are needed to achieve desired resolution for amplitude and transmit equalization control, resulting in larger capacitive load at driver outputs
Solution Approach 1:
The patent merges the functionality of multiple slices into a single DAC by using a high-resolution DAC (e.g., 8-bit or 10-bit) that can directly control amplitude and transmit equalization without requiring multiple lower-resolution slices. This single high-resolution DAC produces fewer output signals with lower individual capacitive loads compared to multiple slices.
4Speed
If conventional TX drivers are used for 112 Gb/s USR applications, then the drivers can handle high data rates, but power consumption and area exceed stringent requirements for ultra-short reach applications
Solution Approach 1:
The patent merges multiple high-power components (multiple serializers, tap-delay data generator, multiple DACs/slices) into a single serializer, analog tap-delay blocks, and a single high-resolution DAC. This consolidation dramatically reduces power consumption while maintaining 112 Gb/s data rate capability through efficient signal processing and minimal capacitive load at the output.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a lower area, power, and capacitance at driver outputs, making the TX driver architecture more suitable for 112 Gb/s USR applications by optimizing power consumption and reducing the number of serializers and tap-delay data generator blocks.
Implementation Method 1
digital-to-analog converter (DAC) circuitry to receive the selected transmit level, convert the selected transmit level to an analog signal of the selected transmit level, and output the analog signal of the selected transmit level over a signal interface
Data Source
AI summary
A method and related apparatus for outputting an analog signal are disclosed. A plurality of transmit levels corresponding to respective predetermined equalization levels is provided. A stream of digital signals carrying data is provided. A transmit level from among the plurality of transmit levels based on the digital signals carrying data is selected. The selected transmit level is received, the selected transmit level is converted to an analog signal of the selected transmit level, and the analog signal of the selected transmit level is output over a signal interface.