TX Driver Architecture for 112 Gb/s USR
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Solution Overview
Problem
Conventional TX drivers for high-speed serial link applications, such as ultra short reach (USR), face challenges in meeting stringent area and power consumption requirements due to high capacitive load and power consumption, making them unsuitable for 112 Gb/s USR applications.
Innovation Solution
A TX driver architecture that includes signal generation, storage, selection, and DAC circuitry with programmable transmit levels, using multiplexers to select and convert digital signals to analog signals with reduced area and power consumption, and fewer serializers to minimize capacitive load.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a conventional DAC based TX driver is used, then the output stage has minimal capacitive load at driver outputs, but the device requires one serializer for every bit of the DAC (e.g., 5 serializers for 5-bit DAC), significantly increasing power and area
Solution Approach 1:
The patent combines multiple serializer functions into a single serializer by using a tap-delay block to generate delayed versions of the input signal. This single serializer outputs multiple signals that are delayed and combined to form the multi-level PAM signal, eliminating the need for multiple separate serializers while maintaining the same output capability.
Solution Approach 2:
The tap-delay block acts as an intermediary component that receives the serialized output and generates delayed versions of the signal. These delayed signals are then combined to create the multi-level PAM output, serving as a mediator between the single serializer and the multi-level signal requirement.
2Area of stationary object
If a conventional tap-delay block based TX driver is used, then the area for DPL/AFE interface is reduced, but the tap-delay data generator block consumes higher power and requires many slices resulting in larger capacitive load
Solution Approach 1:
The patent removes the power-consuming tap-delay data generator block from the system. Instead of generating tap-delay data through a complex data generator, the system uses a simpler approach where the tap-delay block directly processes the serialized output, extracting only the necessary delay functionality while eliminating the high-power data generation component.
3Measurement precision
If many slices are used to achieve desired resolution for amplitude and transmit equalization control, then the resolution is improved, but the capacitive load at driver outputs increases
Solution Approach 1:
The patent uses periodic switching through multiplexers to select between different transmit levels rather than using multiple simultaneous slices. The multiplexers switch between pre-generated PAM4 signal levels based on the input bits, achieving the desired resolution through time-division rather than spatial multiplication, thereby avoiding increased capacitive load.
Data Source
AI summary
An apparatus including a signal generation circuitry to provide a stream of digital signals carrying data. The apparatus includes a storage circuitry to provide a plurality of transmit levels corresponding to respective predetermined equalization levels; selection circuitry to select a transmit level from among the plurality of transmit levels based on the digital signals carrying data. Each of the plurality of transmit levels is a respective input signal to the selection circuitry. The apparatus includes a digital-to-analog converter (DAC) circuitry configured to receive the selected transmit level and convert the selected transmit level to an analog signal of the selected transmit level.