Type I DLL Deskew Circuit for Jitter-Suppressed Clock Output
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Solution Overview
Problem
Type I Delay-Locked Loops (DLLs) face challenges in suppressing jitter, which leads to timing errors due to the amplification of noise as signals propagate through the delay line, causing jitter peaking and making it difficult to maintain phase locking between input and output signals.
Innovation Solution
Incorporating a deskew element that synchronizes transitions between the input and output signals, using a phase detector and loop filter to adjust the delay line, and employing a secondary delay line with sub-interval taps to generate jitter-suppressed clock signals, ensuring the output signal is only propagated when both input and output signals are in the same state, effectively reducing high-frequency jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the delay line is used to phase-match input and output signals in a Type I DLL, then phase locking is achieved, but jitter accumulates and amplifies at the output
Solution Approach 1:
A deskew element is introduced as an intermediary component between the delay line output and the final output. This deskew element receives both the input signal and the delayed output signal, compares their transitions, and only propagates the output when transitions are synchronized, thereby eliminating jitter accumulation while preserving phase matching capability
Solution Approach 2:
The phase detector continuously monitors the phase difference between input and output signals and feeds back control information to the delay line through the loop filter. This feedback mechanism dynamically adjusts the delay to maintain phase locking while the deskew element provides additional feedback to suppress jitter by blocking propagated jitter from affecting subsequent cycles
2Reliability
If bandwidth is reduced to mitigate jitter, then jitter peaking is suppressed, but phase locking responsiveness deteriorates
Solution Approach 1:
The jitter suppression function is segmented from the phase locking function. The loop filter maintains its original bandwidth for fast phase locking, while a separate deskew element handles jitter suppression by synchronizing transitions. This segmentation allows both fast locking and jitter suppression without the trade-off inherent in bandwidth reduction
3Measurement precision
If the delay line length is increased to improve phase matching, then phase locking accuracy improves, but jitter accumulation increases
Solution Approach 1:
The deskew element acts as an intermediary that breaks the direct propagation path of jitter through the delay line. By comparing transitions of input and output signals and only allowing synchronized transitions to pass, it prevents jitter amplification regardless of delay line length, enabling long delay lines for high-resolution phase matching without jitter penalties
Data Source
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AI summary
In one embodiment, a delay-locked loop (DLL) for synchronizing a phase of a periodic digital output signal with a phase of a periodic digital input signal includes a deskew element responsive to the periodic digital input signal to the DLL and the periodic digital output signal from the DLL for suppressing jitter in the periodic digital output signal by synchronizing transitions in the periodic digital output signal with transitions in the periodic digital input signal and generating a final jitter- suppressed periodic digital output signal.