Type I PLL Phase Compensation for Coherent Frequency Jumps
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Solution Overview
Problem
Phase coherence across different frequencies is challenging in phase-based distance estimation applications, particularly in low-IF receivers, as type II PLLs increase lock times, in-band noise, and power consumption, while type I PLLs with pseudo-type II implementations fail to maintain phase coherency across frequency jumps.
Innovation Solution
A method utilizing a type I PLL with an estimated phase correction term ΔΦLO,steady, allowing it to operate as a coherent type 2 PLL, by determining self-resonance frequency, PLL gain, and open-loop gain, and applying corrections through a sigma-delta modulator, eliminating the need for a phase error integration block.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a type II PLL is used to maintain phase coherence across frequencies, then phase coherence is improved, but lock time increases and power consumption increases
Solution Approach 1:
The patent extracts the phase error integration block from the PLL circuit, transforming a type II PLL into a type I PLL. This removal eliminates the inherent phase lag and long lock times associated with integration blocks while maintaining phase coherence through alternative compensation methods described in the patent.
Solution Approach 2:
The patent changes the PLL type parameter from type II to type I, fundamentally altering the system's behavior. This parameter change reduces lock time and power consumption while the patent provides methods to maintain the necessary phase coherence for distance estimation applications.
2Stability of the object's composition
If a type II PLL is used to maintain phase coherence across frequencies, then phase coherence is improved, but power consumption increases
Solution Approach 1:
The patent extracts the phase error integration block from the PLL circuit, transforming a type II PLL into a type I PLL. This removal eliminates the inherent phase lag and long lock times associated with integration blocks while maintaining phase coherence through alternative compensation methods described in the patent.
3Loss of time
If a pseudo type-II PLL is used to achieve fast locking, then lock time is reduced, but phase coherence across frequency jumps is lost
Solution Approach 1:
The patent employs feedback mechanisms to monitor and correct phase errors that occur during frequency jumps. By using feedback to detect phase discontinuities and apply corrections, the system maintains phase coherence across frequency transitions while benefiting from the fast locking characteristics of a type I PLL.
Data Source
AI summary
A type I phase locked loop (PLL) includes an oscillator and a feedback path to a phase detector. The PLL is configured to lock a first frequency and first relative phase of a first output signal to a frequency and a phase of a first input signal, and lock a second frequency and second relative phase of a second output signal to a frequency and a phase of a second input signal. A steady state phase lag of the PLL resulting from the difference between the first frequency and the second frequency is estimated, and the estimated steady state phase lag is used to determine a total phase shift (ΔΦLO,steady) between the second input signal and the second output signal. The PLL for the phase shift can be compensated. The determined total phase shift can be used in a distance estimation.