Type I PLL Loop Filter for Fast Settling and Spur Reduction

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Solution Overview

Problem

Phase locked loop circuits face a trade-off between settling time and spectral purity, with type II PLLs effectively suppressing spurious components but introducing instability and overshoot, which limits the number of usable time slots in time division multiplexing radio systems.

Innovation Solution

A type I phase locked loop design with a low pass filter and a voltage controlled oscillator, where the loop filter is an all-pole filter with a selected prototype order that optimizes settling time and minimizes spurious frequency components, using a Gaussian filter to achieve a balance between settling time and spur reduction.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-generated harmful factors

If type II phase locked loop architecture with two integrators is used, then spurious components are suppressed, but settling time increases and stability is compromised

Engineering Contradiction:

Improvespurious componentsVSAvoidsettling time

Core Design Contradiction:

Object-generated harmful factorsVSLoss of time

Solution Approach 1:

The patent changes the fundamental parameters of the PLL architecture from type II to type I, reducing the number of integrators from two to one. This parameter change fundamentally alters the loop transfer function, eliminating the stability issues and excessive settling time while maintaining effective spurious component suppression through optimized loop filter design.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent extracts one integrator from the type II PLL architecture, leaving only a single integrator in the type I configuration. This extraction removes the conflicting requirements for stability and fast settling while preserving the essential frequency synthesis functionality.

Inventive Principle:

Principle #2Taking out (Extraction)

2Object-generated harmful factors

If type II phase locked loop with two integrators is used, then spurious components are suppressed, but system stability deteriorates

Engineering Contradiction:

Improvespurious componentsVSAvoidsystem stability

Core Design Contradiction:

Object-generated harmful factorsVSStability of the object's composition

Solution Approach 1:

The patent changes the integrator count parameter from two to one, fundamentally altering the loop transfer function characteristics. This parameter change eliminates the stability compromise inherent in type II designs while maintaining effective spurious component suppression through the optimized type I architecture with appropriate loop filter design.

Inventive Principle:

Principle #35Parameter changes

3Object-generated harmful factors

If conventional loop filter design is used, then spurious reduction is achieved, but settling time is prolonged

Engineering Contradiction:

Improvespurious componentsVSAvoidsettling time

Core Design Contradiction:

Object-generated harmful factorsVSLoss of time

Solution Approach 1:

The patent optimizes the loop filter parameters specifically for type I PLL architecture, adjusting the filter order and characteristics to achieve the optimal balance between spurious component suppression and fast settling time. This parameter optimization is tailored to the single-integrator type I configuration rather than conventional type II designs.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design allows for faster tuning of the phase locked loop, enabling all time slots to be used in time division multiplexing radio systems without blind slots, thereby increasing the number of connected portable devices while maintaining sufficient spur reduction.

Implementation Method 1

The loop filter 20 generates a control signal that varies the frequency of the adjustable frequency oscillator 25

Methodology Applied

Scientific EffectFiltering: Filter (electronic)

Implementation Method 2

The output of the adjustable frequency oscillator 25 is the output signal FOUT

Methodology Applied

Scientific EffectVoltage-controlled oscillation:

Data Source

PatentUS9473156B2Fast settling phase locked loop (PLL) with optimum spur reduction

Publication Date: 2016.10.18 DIALOG SEMICONDUCTOR BV

AI summary

A method for constructing a phase locked loop begins with determining spurious frequency component criteria permitted within the PLL. A PLL filter prototype is selected with a desired settling time. A transfer function is generated based on the PLL transfer function that predicts the spurious components. A maximum level of the spurious components produced in the PLL is determined based on the maximum frequency step. If the maximum level of the spurious frequency components produced is too large, the order variable is incremented and the PLL transfer function is determined until the transfer function produces the spurious frequency components that meet the requirements. The components for a loop filter are selected based on the selected PLL transfer function. The adjustable frequency source tuning gain, the phase detector gain, the loop filter gain, and the divide factor are chosen to meet the requirements of the PLL transfer function.