Type-I PLL Gating to Prevent Sub-Harmonic Locking
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Solution Overview
Problem
Conventional type-I phase locked loops (PLLs) suffer from sub-harmonic locking, where they lock to a frequency that is a sub-harmonic of the oscillator output signal, leading to instability and inefficiency, particularly due to the use of large capacitors that increase die costs and cause leakage current issues in deep sub-micron CMOS processes.
Innovation Solution
A type-I PLL design that includes a phase frequency detector (PFD) with a gating element to control the charging and discharging of capacitors, preventing sub-harmonic locking by generating a clear output signal to discharge the sampling capacitor only during specific time periods, thus maintaining the voltage-controlled oscillator at the intended frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a large capacitor is used in a type-II PLL to improve stability, then the stability of the loop is improved, but the die cost increases and leakage current issues occur in deep sub-micron CMOS processes
Solution Approach 1:
The loop filter is segmented into multiple capacitors (first capacitor, second capacitor, third capacitor) with different functions. The first capacitor provides stability while the second and third capacitors control charging/discharging timing to prevent sub-harmonic locking, allowing stability without requiring a single large capacitor
Solution Approach 2:
The patent implements periodic charging and discharging of capacitors through controlled time periods. The second capacitor charges during a first time period and discharges during a second time period, creating periodic action that maintains stability while preventing sub-harmonic locking and reducing leakage current
2Device complexity
If conventional type-I PLL operation is used to simplify the circuit, then the circuit complexity is reduced, but sub-harmonic locking occurs where the PLL locks to a sub-harmonic frequency
Solution Approach 1:
The patent implements preliminary action by controlling the charging and discharging timing of capacitors before sub-harmonic locking can occur. The gating element prevents capacitor discharge during specific time periods when sub-harmonic locking would occur, proactively preventing the problem rather than correcting it
Solution Approach 2:
The phase frequency detector provides feedback by generating a gating signal that controls the charging and discharging of capacitors based on the phase difference between reference and divider clock signals. This feedback mechanism ensures the PLL locks to the fundamental frequency and prevents sub-harmonic locking
Data Source
AI summary
Embodiments relate to type-I PLLs that do not lock at a sub-harmonic frequency of a reference clock signal by controlling timing of charging or discharging of one or more capacitors in the PLLs. A phase frequency detector (PFD) of a type-I PLL can prevent sub-harmonic locking by generating a clear output signal to cause a sampling capacitor of PLL's loop filter to discharge only during a time period when the sampling capacitor is not being charged. For example, the PFD can include a gating element to control the time during which the clear output signal is generated. By ensuring that the sampling capacitor is not discharged during a time period while it is being charged, the PLL's voltage-controlled oscillator is controlled to oscillate at an intended frequency rather than at a sub-harmonic of the intended frequency.